darrell@sdcsvax.UUCP (04/23/87)
In article <3027@sdcsvax.UCSD.EDU> stuart@CS.ROCHESTER.EDU (Stuart Friedberg) writes: >Prodded by something Avie Tevanian of the MACH research group said, >I have been considering life with a translation lookaside buffer (TLB) >but without hardware page tables (PT). This message is intended to >spark some discussion of a) what such a system would be like, One way it could look is like the Celerity Accel. It provides a very large, software managed TLB which we call an "Address Translation Cache". The Address Translation Cache is a 4096 or 16396 entry "four way associative" memory. Each entry contains the complete virtual address (including process identifier), the real page number and the access permissions. Address translation proceeds as follows: the virtual address is hashed to select a four entry "bank" which is examined for a match to the virtual address. If there is a matching entry then the real address and access permissions are taken from that entry. If there is no match then a trap occurs for software to load one of the four entries selected by the virtual address and retry the operation which failed. Software could maintain a page table and use that to find the virtual to real mapping to be loaded into the cache. However, we maintain a linked list for each cache bank which contains the entries which would be present if bank were indefinitely deep. After an Address Translation fault, the hardware supplies the hashed address so that the appropriate list can be found quickly. The key to speed with this technique is the size of the cache so that translation faults occur rarely and the fact that it contains a process identifier so that it is seldom invalidated. -- J. J. Whelan Celerity Computing