veit@du9ds3.uni-duisburg.de (Holger Veit) (06/06/91)
Some of the ISCAS'89 benchmark circuits were created by a synthesis algorithm from a high level description. Examples are s208, s838, s344 and (probably) s1423. Some of them also have a distinct "function" that can be expressed by few statements in a HL form. Examples are again s208 (8 bit programmable clock divider), s838 (32 bit version of s208) and s344 (4x4 Bit shift&add multiplier). Automated test patteren generation (especially for sequentially deep circuits) would be easier if the function were known. This is the main advantage a test engineer has: he knows how the circuit has to be initialized, driven, what's observable, etc. Are there HL descriptions (in any HDL for instance: VHDL,Verilog,ISPS,etc.) for at least some of the benchmark circuits (I know that the largest circuits were real designs but were modified by exchange of components, so there are none with exact function). This request goes especially to the (anonymous) contributors of the circuits. Please help. Holger Veit -- | | / Holger Veit | INTERNET: veit@du9ds3.uni-duisburg.de |__| / University of Duisburg | BITNET: veit%du9ds3.uni-duisburg.de@UNIDO | | / Fac. of Electr. Eng. | UUCP: ...!uunet!unido!unidui!hl351ge | |/ Dept. f. Dataprocessing |
allison@convex.com (Brian Allison) (06/07/91)
In article <veit.676191831@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes: > >Some of the ISCAS'89 benchmark circuits were created by a synthesis [...] >Are there HL descriptions (in any HDL for instance: VHDL,Verilog,ISPS,etc.) >for at least some of the benchmark circuits (I know that the largest circuits >were real designs but were modified by exchange of components, so there are >none with exact function). > >This request goes especially to the (anonymous) contributors of the circuits. > >Please help. > >Holger Veit Your best bet, if you haven't done this already, may be to check with Franc Brglez, David Bryan, or Krzysztof Kozminski at MCNC (brglez@mcnc.org, bryan@mcnc.org, or kk@mcnc.org). They may not be reading this newsgroup since it's so new. -- Brian Allison "If pro and con are opposites, is Convex Computer Corp. Congress the opposite of progress?" Richardson, TX - Richard Lederer
lee@pipe.cs.wisc.edu (Soo Lee) (06/07/91)
In article <1991Jun06.174451.14437@convex.com> allison@convex.com (Brian Allison) writes: >In article <veit.676191831@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes: >> >>Some of the ISCAS'89 benchmark circuits were created by a synthesis >[...] >>Are there HL descriptions (in any HDL for instance: VHDL,Verilog,ISPS,etc.) >>for at least some of the benchmark circuits (I know that the largest circuits >>were real designs but were modified by exchange of components, so there are >>none with exact function). >> >>This request goes especially to the (anonymous) contributors of the circuits. >> >>Please help. >> >>Holger Veit > >Your best bet, if you haven't done this already, may be to check with >Franc Brglez, David Bryan, or Krzysztof Kozminski at MCNC (brglez@mcnc.org, >bryan@mcnc.org, or kk@mcnc.org). They may not be reading this newsgroup >since it's so new. >-- >Brian Allison "If pro and con are opposites, is >Convex Computer Corp. Congress the opposite of progress?" >Richardson, TX - Richard Lederer Try anonymous ftp to mcnc at the following ftp address, mcnc.mcnc.org Soo lee@cs.wisc.edu
kk@mcnc.org (Krzysztof Kozminski) (06/08/91)
In article <veit.676191831@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes: > >Some of the ISCAS'89 benchmark circuits were created by a synthesis >algorithm from a high level description. Examples are s208, s838, s344 >and (probably) s1423. Some of them also have a distinct "function" that can >be expressed by few statements in a HL form. Examples are again >s208 (8 bit programmable clock divider), s838 (32 bit version of s208) and >s344 (4x4 Bit shift&add multiplier). Also: s420 - 16-bit version of the clock divider (the circuit description can be found in "Intro to Computer Logic" by H.Troy Nagle et al. Prentice Hall 1975, p. 461. Signal W is the carry-out from the counter. Other signals are as in the book. I have descriptions of s208, s420, and s838 in a Pascal-like structural/functional language LOGIC-3, with comments. s953 - this is a controller taken out of a chip designed at Duke Univ. I might be able to retrieve its description in LOGIC-3, but it will take some time to go through the archival tapes (the chip went through several design iterations and, at the first glance, I can't seem to find the one used for the benchmark...). s349 - same as s344, except has a couple of redundancies. I believe that for a couple of other circuits (s1494 and s1488), we have transition tables of the FSMs - I'll have to check it. Also, I'll relay the request for HL-descriptions to the contributors of the benchmarks. I'll have some more info after DAC ... KK -- Kris Kozminski kk@mcnc.org "The party was a masquerade; the guests were all wearing their faces."