dettmer@jupiter.informatik.uni-dortmund.de (Thomas Dettmer) (01/10/91)
The following article is forwarded from comp.lsi.
Does anybody know an ftp adress or some more about this? adress?
************************ article from comp.lsi ****************
After several inquiries, I realized that I'd better post this on
the net rather than try individual replies:
Here is the README file from the University of Pittsburgh simulator.
It has the names of the developers, I guess they can be contacted
regarding how to obtain a copy of the software.
>From what I could find out - Syracuse Universiry paid about $75
for the simulator - probably a s/h + cost of tape charge.
Shantanu Ganguly
Syracuse University
sganguly@cat.syr.edu
-----------------README FILE--------------------------------------
Last Modified: 2/6/90 -- Alan R. Martello, University of Pittsburgh
OVERVIEW
--------
This is the README file for the VHDL toolset distriuted by the
University of Pittsburgh. The tools currently supported are a VHDL
1076 Compiler and a Simulator.
The compiler parses (hopefully) the entire 1076 syntax. A database
is built from a subset of the VHDL parsed (the VHDL which is parsed
but not built into the database is thrown out after warnings are
generated). The subset of VHDL parsed is discussed in the man pages.
An event driven simulator exists which can read the database generated
and allow for simulation of the output network. The tools simulate
both concurrent and sequential VHDL. The concurrent VHDL is simply
built into a network of gates and the sequential VHDL is translated to
'C' code. To perform a simulation utilizing sequential code, a new
simulator must be linked to include the translated constructs.
PLATFORM
--------
The only platform totally supported is the SUN-3 series (since these
are the computers used for the code development). However, we attempt
to allow the tools to be run on a variety of platforms. All the tools
are textual and may be run on "dumb" terminals. The tools have been
known to work on the following platforms:
- Sun-3
- Sun-4
- VAX/VMS
- VAX Ultrix
- Apollo
PORTING
-------
The code has been written in fairly generic 'C' and should be easily
portable to any "standard" (Berkley/4.2) Unix environment. A System V
port should not be much of a problem, the only troublesome area should
be "strings.h".
All I/O is done via "standard" Unix calls and any Unix compatible
library should suffice. There has been substantial interest in a PC
port of the tools. However, this is not currently being attempted by
us.
The standard Unix YACC could not be used to generate the VHDL parser
due to the number of production rules associated with the grammar.
Instead, we use the GNU tool Bison to compile the grammar and create
the parser tables. We find this tool more robust, reliable, and
faster than YACC.
The tools assume that they are running in a "virutal" environment
since the parser generated by Bison is extremely large and each data
structure in the threaded database graph generated is allocated
dynamically.
If you have successfully ported the tools to another environment, we
are interested in receiving a description of the environment (along
with any code modifications). Bug fixes and enhancements are made as
time permits and this allows for continued support of multiple
platforms.
DISCLAIMER
----------
This code has evolved over the past few years from a Master's thesis
to a PhD project. In the process, it has undergone at least one
substantial rewrite and variaous areas have been greatly reworked.
The work in its current form has NOT been supported directly either by
the University of Pittsburgh or by any outside funding. As such,
enhancements and bug fixes are only performed to further our current
research goals.
NOTE: these tools are
Copyright 1989-1990 University of Pittsburgh and Alan R. Martello
and as such, may NOT be sold either in whole or part without the
written consent or the authors.
SOURCE STRUCUTRE
----------------
The following files and directories are of particular interest:
README this file
INSTALLATION installation notes
VERSION_HISTORY a chronological history of the compiler
development, a MUST for anyone
modifying the code.
COPYRIGHT the Copyright notice
NO_WARRANTY our NO WARRANTY statement
bison.tar a 'tar' file of Bison for those without it
source directories of interest:
exaples/ a few examples
doc/ the (scarce) documentation
vsim/ the simulator source
vcomp/ the compiler source
include/ include files used by both the compiler and
simulator
VMS_BIN/ misc. files used for running under VMS
bin/ place where the installed binaries live
lib/ place where the vsim library lives
THANKS
------
Thanks to:
Bob Owens at Penn State University
Kevin J. Buchs at Mayo Foundation
***************** end of article from comp.lsi ***********
dettmer@jupiter.ls1.informatik.uni-dortmund.de
phone: +49-231 755 4825, FAX: +49-231 755 2386
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germanyvhdl@ee.pitt.edu (vhdl tools pseudo-user) (01/11/91)
Thought I'd post the latest information on our VHDL tools.
*************************************************************
* This is the file README available by anonymous ftp from *
* ee.pitt.edu (130.49.15.1) in pub/vhdl-info *
*************************************************************
This directory pub/vhdl-info contains the following files:
File Description
---- -----------
README this file
letter.txt instructions on how to order the VHDL software
barrel.vhdl a trivial example of a barrel shifter
pulse.vhdl a 3-gate pulser
mult.vhdl three examples of a shift and add multiplier
All of the files listed below are in Postscript form.
license.PS license agreement for the software
assurance.PS export assurance letter for the software
vcomp.PS man page for the VHDL compiler
vsim.PS man page for the VHDL simulator
waveform.PS man page describing how to generate ascii waveforms
ivf.PS man page describing the
tech_report.PS a paper which details some implementation details
of the vhdl compiler and simulator
main_vhdl_over.PS set of slides providing an overview of VHDL
main_vhdl_syntax.PS set of slides illustrating VHDL supported
vhdl.1-23.PS set of slides on basic vhdl usage with examples
----------------------------------------------------------------------
Dear Sir or Madam:
I am writing to let you know that we are ready to release the new
version of our VHDL tools. The two main tools are vcomp, a VHDL 1076B
parser-compiler, and vsim an interactive simulator. Vcomp parses the
complete language but only generates output for a small, but useful,
subset of the language. Process statements are compiled into C source
code for run time linking with the simulator vsim. We are including
source code in this distribution, including all the parsing tables
etc. We have used bison, the GNU version of yacc for our parser. We
also are distributing a small set of examples and some "courseware"
which we use when we lecture to our students about VHDL in our digital
design and VLSI courses.
The software is all "Copyright University of Pittsburgh" and we are
issuing a non-exclusive, non-transferable license, the software is not
"public domain". Our purpose is to let more people have access to the
VHDL language for experimentation and research, not to support
commercial products.
We are distributing the software on Sun cartridge tapes for a fee of
$150. Tapes will be written in "Unix tar" format. Unfortunately, we
do not have the staff to answer phone questions. We will try to
respond to computer and U.S. mail requests. If you want a copy of the
tools, please read and sign the accompanying license agreement and
letter of assurance, and send a check made out to "Department of
Electrical Engineering, University of Pittsburgh" for $150 to:
Prof. Steven Levitan
Department of Electrical Engineering
348 Benedum Engineering Hall
University of Pittsburgh, 15261
Internet: vhdl@ee.pitt.edu
Just to let you know, we are currently working with our colleagues at
Penn State University to broaden the set of tools we will distribute
to include the rest of the Keystone synthesis tools, these allow our
students to go from VHDL into CMOS VLSI layouts, I will let you know
when that extended package is available and how to get that in the
near future.