petera@chook.adelaide.edu.au (Peter Ashenden) (01/17/91)
Just an idle question: Can someone tell me what the purpose of ports of modes linkage and buffer is? They're not really covered in any of the books I've read, the standard doesn't help, and the models I've written haven't suffered from not using them (so far as I know). Curious. Peter A ---------------------------------------------------------------- Peter J. Ashenden Dept. Computer Science, University of Adelaide, South Australia
rose@SRC.Honeywell.COM (Fred Rose) (01/17/91)
In article <2267@sirius.ucs.adelaide.edu.au> petera@chook.adelaide.edu.au (Peter Ashenden) writes: Peter> Can someone tell me what the purpose of ports of modes linkage and Peter> buffer is? They're not really covered in any of the books I've read, Peter> the standard doesn't help, and the models I've written haven't suffered Peter> from not using them (so far as I know). Buffer mode is the same as mode inout, except that a buffer may have at most one source. This is useful in the case of a gate driving a signal that is an output of the component (entity/architecture) but the signal also feedsback into the component and drives another gate. This signal can also be called mode inout but that designation does not really describe what is happening, because this is not a tru bi-directional port. Think of this schematically, which is where it happens frequently, and it becomes clearer. Signal_out is being driven by Gate_a but also feeds back to Gate_b. It is really an output of this component but calling it mode out is illegal. Calling it mode inout is legal but that implies that something on the outside can drive signal_out. That is not the intent, hence mode buffer. +----+Gate_a | | | |out |-------------|---------> Signal_out | | | | +----+ | | port mode buffer ----------- | ---- Gate_b | | | | | | -- |in | ---- Another solution to this problem gate_a_out <= gate_a_in1 or gate_a_in2; --Gate A is an OR gate for the sake of --argument signal_out <= gate_a_out; gate_b_out <= not gate_a_out; -- Gate B is an Inverter Then the port mode may be called mode out. Disadvantage is the introduction of an additional signal (gate_a_out) and delta delay. Both solutions work,the one chosen is a matter of preference and compatibility with the design process. Port mode linkage is for connecting to non-VHDL routines, or if you don't know what the actual port type will be. --------------------------------------------------------- Fred Rose Honeywell Systems and Research Center MS-2100 e-mail: rose@src.honeywell.com 3660 Technology Dr. Phone : (612) 782-7106 Minneapolis, MN 55418 Fax : (612) 782-7438