[comp.lang.vhdl] VHDL standard value logic packages

jackg@bears.UCSB.EDU (Jack Greenbaum) (01/22/91)

Does anyone have information on the IEEE's proposed standard logic
value package? I have heard that IEEE and EIA are working on
standards. I would like to get a hold of the IEEE package if it is
available.

-- 
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Jack Greenbaum      |University of California, Santa Barbara
jackg@bears.ucsb.edu|Department of Electrical and Computer Engineering, Box 253
                    |Santa Barbara, Ca. 93106
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koo@tcville.HAC.COM (01/25/91)

> Does anyone have information on the IEEE's proposed standard logic
> value package?  I have heard that IEEE and EIA are working on
> standards.  I would like to get a hold of the IEEE package if it is
> available.

I assume you already know about the EIA standard packages.

I haven't heard of an IEEE package, but the IEEE WAVES (Waveform And
Vector Exchange Specification) standardization group is distributing a
set of WAVES packages for ballotting.  I don't know if this is what
you are looking for, so the info is brief:

  A package called WAVES_SYSTEM allows you to represent almost all
  logic states currently used by simulators and testers.  The purpose
  of this is to allow you to represent the logic values used by your
  simulator (or tester) accurately, and transport them correctly to
  another simulator or tester.

  The structure is not simple, but it allows you to represent more
  exotic logic states (e.g.  'valid' = logic 0 and logic 1, but not
  midband).  Documentation is available in the form of IEEE WAVES
  ballotting documents.

Hope this helps,

    Frances (koo@tcville.hac.com)