cees@maestro.htsa.aha.nl (Cees Keyer) (01/31/91)
Hello netlanders, We are trying to set up a course in VHDL. So we would like to have a overview on the software which is available in the Public Domain. So if any one knows about PD software which can handle VHDl circuit descriptions and simulate or parse them please let me know. I'll post an article with the replies I'll get. Thanks in advance, Cees Keyer. -- Ach, ik ben slechts een a-modieus wezen, gedrenkt in de pap der tijden. Cees Keyer, Algemene Hogeschool Amsterdam. | fax: (+31) 20-443215 department of electrical engineering. | phone (+31) 20-429333 Email: cees@maestro.htsa.aha.nl cees@tamtam.htsa.aha.nl Snail: AHA-TMF, Europaboulevard 23, 1079 PC Amsterdam, The Netherlands.
cees@maestro.htsa.aha.nl (Cees Keyer) (02/11/91)
Netlanders, Here is the summary on the VHDL public domain software request. >From: Thomas Dettmer <dettmer@jupiter.informatik.uni-dortmund.de> > >What is your timing to set up the course? We are currently implementing a >graphical VHDL editor (based on X11R4, Sparc-Station) and plan to give it in >the PD (as executable, not sources). If my professor agrees :-). It is >developed in a diploma thesis which will be finished in 5'91. >It'll in its first versions a one way solution: >You create your description with a schematic-like interface, which supports >libraries, entities with ports, structural architecture descriptions and >some parts of behavior (all graphic). It can store in an internal format >(including the graphic) or produce VHDL source to fill in other information. >There is no way back from VHDL-Code to graohics currently. >Interested? > >tom. -- dettmer@jupiter.ls1.informatik.uni-dortmund.de phone: +49-231 755 4825, FAX: +49-231 755 2386 Thomas Dettmer, Dortmund University, Computer Science I Post Box 50 05 00, W-4600 Dortmund 50, Germany ____________________________NEXT_______________________________________ From: pmayor@cat.syr.edu (Pankaj Mayor) Try the toolset from University of Pittsburgh. For more info write to vhdl@ee.pitt.edu. From uucp Thu Jan 31 20:15:18 1991 Status: R From: Suresh Rajgopal <rajgopal@cs.unc.edu> > I am aware of a VHDL parser written in Prolog which can also be used to answer simple design queries. It is public domain. The person who wrote it can be reached at: quintus!pbr@sun.com His name: Peter Reintjes Cheers -Suresh ____________________________NEXT_______________________________________ From: David C Blight <blight@eeserv.ee.umanitoba.ca> University of Manitoba has developed a VHDL program which accepts VHDL structural descriptions and produces EDIF netlist which are used with the Cadence IC design software. Soon the software will support XILINX (programable gate arrays) designs. Behavioral simulation is supported for a subset of the VHDL language (enough to simulate structural descriptions). The programs may soon be expanded to cover the rest of the language. Information may be obtained from blight@eeserv.ee.umanitoba.ca -- David C Blight blight@ee.umanitoba.ca Dept of Electrical and Computer Engineering (204) 261-3919 University of Manitoba (204) 261-4639 (FAX) Canada ____________________________NEXT_______________________________________ From: John.Willis@FAS.RI.CMU.EDU I am in the testing phase for Auriga, an optimizing compiler for parallel simulation of VHDL. Auriga is based on the GNU C compiler machine dependent components. A validated version should be available for use by September of 1991. If you provide a physical mail address, I will send reprints and put you on our mailing list. -John ____________________________NEXT_______________________________________ From: Gordon Newell <newell@Corona.ITD.MsState.Edu> I saw your posting on info-vlsi, and although I do not know of any public-domain VHDL software (analyzer and simulator), we do have a set of VHDL SSI models available to the public (as Mr. Barton said). I'm including with this message some information about the models. I do believe, however, that the MCC simulator is available to universities for a very small charge. Bill Read is in charge of the MCC simulator. Here is his address: Bill Read MCC VHDL Simulator (512)338-3513 Bill Read 3500 W. Valcones Center Dr. Bill Read Austin, TX 78759 Bill Read Email : read@mcc.com _______ / | ================================/ |=================================== | Gordon Newell /Starkville Internet:newell@itd.msstate.edu| | VHDL Modeling Group / * | Phone: (601)325-2240 | | Institute for Technology Dev \ | FAX: (601)325-8144 | | 1 Research Blvd | | | | Starkville, MS 39759 / | | ===============================/ |=================================== |______ | / | \____| VHDL SSI TTL Component Library Revision 2.1 available from: The Institute for Technology Development Center for Military Replacement Parts VHDL Modeling Group Component Library Models: AM2901C SN54368 SN5438 SN54LS00 SN54LS04 SN54LS109 SN54LS112 SN54LS161 SN54S00 SN54S02 SN54S04 SN54S08 SN54S11 SN54S112 SN54S138 SN54S140 SN54S175 SN54S251 SN54S280 SN54S86 Modeling Standards: VHDL Data Item Description DI-EGDS-80811 Waveform And Vector Exchange Specification WAVES PAR 1029.1/D1 Model Features: Full Timing Modules WAVES Test Benches Proposed IEEE 9-State Multi-Valued Logic System Component Library Cost: $25 tape shipping and handling fee ($50 for shipments outside the U.S.) Contact: Gordon Newell ITD/VHDL Modeling Group 1 Research Blvd. Starkville, MS 39759 (601)325-2240 Email: newell@itd.msstate.edu The Institute for Technology Development Center for Military Replacement Parts VHDL Modeling Group VHDL SSI TTL Component Model Library Order Form $25.00 tape shipping and handling fee ($50.00 for shipments outside the U.S.) Name: __________________________________________________ Title: __________________________________________________ Company: __________________________________________________ Address: __________________________________________________ __________________________________________________ Phone: __________________________________________________ email address: __________________________________________________ Tape Media: 1/4" cartridge____ 1/2" reel-to-reel____ ARPANET____ Revision: 2.1 Tape Format: UNIX tar Payable to: Institute for Technology Development 1 Research Blvd. Starkville, MS 39759 attn: Gordon Newell (601)325-2240 ____________________________NEXT_______________________________________ } A real good source is the package of basic gates distributed for a } copying charge by ITD, associated with Mississippi State in } Starkville, Miss. Not only is this a good selection of basic gates, } but it conforms to the preliminary standards under consideration by } the EIA and the modeling standards committee of the IEEE DASS. } Contact ITD at Starkville (I do not have the number; try long distance } information). } } Dave Barton } barton@i2wash.com }-- End of excerpt from davidb@inmet.inmet.com Our VHDL modelling group here at ITD is headed by Scott Calhoun. You can reach him through email by jscott@itd.msstate.edu or by phone: (601)-325-8356 **************************************************************** * Robert Miller (socrates@itd.msstate.edu) * * CAD/System Administrator * * Institute for Technology Development * * Advanced MicroElectronics Division * * 1 Research Blvd. Suite 205. * * Starkville, Ms. 39759 * **************************************************************** These are the replies i've got. Some replies i've left out because the were refering to the same software. Thanks again for all the replies Cees Keyer. -- Ach, ik ben slechts een a-modieus wezen, gedrenkt in de pap der tijden. Cees Keyer, Algemene Hogeschool Amsterdam. | fax: (+31) 20-443215 department of electrical engineering. | phone (+31) 20-429333 Email: cees@maestro.htsa.aha.nl cees@tamtam.htsa.aha.nl Snail: AHA-TMF, Europaboulevard 23, 1079 PC Amsterdam, The Netherlands.