[comp.lang.vhdl] VHDL-Forum for CAD in Europe

dettmer@jupiter.informatik.uni-dortmund.de (Thomas Dettmer) (02/18/91)

		VHDL-Forum for CAD in Europe

     		    SPRING '91 MEETING

	April, 24-26, 1991, IMT, Marseille, France

VHDL-Forum for CAD in Europe:  The VHDL-Forum for CAD in Europe is the
European VHDL Users' Group  active in VHDL related Topics &
Standardization Efforts and was founded at the IFIP VLSI'89 in Munich.
The members belong to an international range of companies, institutes
and universities, VHDL users as well as VHDL vendors. The motivation
and history of the group was the European diverse experience in the
field of HDLs
& related topics (description, simulation, synthesis, formal proof &
verification,...). The VHDL-Forum is related to the VHDL Users' Group
(US) and to the different VHDL standardization groups (DASS, European
WG on VHDL Standardization). The previous meetings (Fall'89 (Munich),
Spring'90 (Grassau/Munich), Fall'90 (EUROVHDL, Marseille) have shown
great interest in the activities of this group.

Immediately preceding the VHDL-Forum Spring '91 Meeting, and organized
at the same location in close cooperation, the IFIP CHDL '91 (Tenth
International Symposium on Computer Hardware Description Languages and
their Applications) will be held.  Common sessions are scheduled for
April 24 in the
afternoon. Because of the complementary nature of both events,
VHDL-Forum being more specialized and user oriented, CHDL being more
general and research oriented, we encourage visitors to attend both.
In registering to both at the same time, you will save administrative
costs. The Spring '91 Meeting is sponsored by the International
Federation for Information Processing IFIP WG
10.2/10.5. Hosted by Institut Mediterraneen de Technologie.

General Chair:  Andreas Hohl, SIEMENS, FRG

Program Committee:  D. Borrione, France, A. Hohl (Chair), FRG, J.
Mermet, France, G. Musgrave,  U.K., A. Postula, Sweden, F. Rammig,  FRG

Conference Secretariat: 
SUD CONGRES SERVICES-CHDL/VHDL 277, Chemin du Vallon de l 'Oriol
13007 Marseille (France) 
Phone: +33-91 59 43 33         Fax:    +33-91 52 63 68


				Meeting Agenda

Wednesday, April 24th, 1991

10.00   Registration

12.30   Lunch

14.00   Welcome & Common Sessions with IFIP CHDL'91
	VHDL-Forum for CAD in Europe: The European VHDL Users' Group A.
	Hohl, SIEMENS, FRG 17.30

Thursday, April 25th, 1991

9.00    Session 1, Simulation
	(Chair: G. Musgrave, Brunel University, U.K.)

	The Requirements For Analog And Mixed-mode Simulation in VHDL
	C. Le Faou, IMAG/ARTEMIS, France, J. Mermet, IMT, France

	Language Concepts For Analog Circuit Description In VHDL R.
	Boute, Univertiy of Nijmengen, The Netherlands

	Non Linear Interpolator: A Behavioral Simulation Using VHDL
	Language, P. Piccinelli, M.G. Podesta', F. Scalise,
	SGS-Thomson, Italy

	Simulation Of Analog Circuits Using VHDL D. Rouquier, CNET/CNS,
	France

10.30   Coffee Break

11.00    Session 2,     Environments
	(Chair: A. Oczko, CADLAB, FRG)

	Analysing VHDL-Programs T. Dettmer, Dortmund University, FRG

	Software Engineering In High Level Synthesis J. Benzakki, M.
	Israel, IIE-CNAM, France

	ASIC Design And VHDL, Library Portability: A Standard
	Approach?  P. Guiraudou, ARCAD, J.-P. Caisso, E. Garcia, MATRA
	MHS, France

	SUVHDLIG - The Soviet Union VHDL Interest Group U.A.
	Tartarnikov, L.G. Titarev, USSR

12.30   Lunch

14.00   Panel Session
	A VHDL Simulation System For The CAE Tool Builder R. Kupyn,
	CLSI, U.K.

	 "VHDL within the Design Process: Benefits, Problems and
	 Solutions"     (Chair: A. Hohl, SIEMENS FRG)

15.00   Coffee Break

15.30   Working Groups

	Synthesis (Chair: A. Postula, Swedish Institute of
	Microelectronics, Sweden) Modelling Techniques in VHDL ( Chair:
	A. Pawlak, G.M.D. Project E.I.S., FRG) VHDL and System Level
	Descriptions (Chair: A. Oczko, CADLAB, FRG)

17.00  - 17.30  Results from the Working Groups 20.00  -  22.30 Banquet

Friday, April 26th, 1991 9.00     Session 3, Modeling & Verification
	(Chair:  J. Mermet, IMT, France)

	Formal Reasoning About Signal Attributes In VHDL A. Salem, D.
	Borrione, IMAG/ARTEMIS, France

	Task Level Behavioral Description Translation To IEEE VHDL
	L.P.M. Benders, Open University of Heerlen, M.P.J. Stevens,
	University of Eindhoven, The Netherlands

	A Methodology For Standard Component Models Definition J.-L.
	Dubois, University of Lille, France, A. Pawlak, G.M.D.  Project
	E.I.S., FRG

	A Technique For Modelling Standard Cells In VHDL M. Bl?uml, M.
	Lenzen, A. Pawlak, G.M.D. Project E.I.S., FRG 10.30   Coffee
Break

11.00   Panel Session
	New Synthesis Options From VHDL J. Saunders, ED, U.K.

	"VHDL and Synthesis: Benefits, Problems and Solutions"
	 (Chair: A. Postula, Swedish Institute of Microelectronics,
	 Sweden)

12.00   Closing Session
	(Chair: A. Hohl, SIEMENS FRG)

	VHDL Reballot 1992 ( J. Rouillard, IMT, France)

	Announcements On VHDL Activities

12.45   Lunch

14.00   VASG Meeting

	Open Meeting of the DASS VHDL Analysis and Standardization
	Subcommittee

_____________________________________

CONFERENCE REGISTRATION FEES

				Received                Received after
				before                  March 15.'91or
				March 15.'91            at Conference
VHDL-Forum only (April 24-26)
 Member IFIP or affiliated       1700 FF                 2100 FF
 Organisation (*) 
 Non-member                     1900 FF                  2300 FF

CHDL'91 only (April22-24) 
 Member IFIP or affiliated       1900 FF                 2300 FF
 Organisation (*) 
 Non-member                      2100 FF                 2500 FF

CHDL '91 & VHDL-Forum (April 22- 26) (120 FF discount) 
Member IFIP or affiliated        3480 FF                 4280 FF
Organisation (*)
Non-member                       3880 FF                 4680 FF

(*)IEEE, ACM, IEE, BCS, SEE, AFCET The above fees include admission to
all technical sessions and exhibitis, the Sunday Cocktail, the Banquet
(Tuesday for CHDL '91 and Thursday for Forum), morning and afternoon
refreshments, lunches, a copy of  the conference proceedings and the
shuttle bus service.

PAYMENT OF CONFERENCE FEES Cheques in French Francs should be payable
to:  Sud CONGRES SERVICES-CHDL/VHDL 277, CH du Vallon de l'Oriol 13007
Marseille (France) Credit card facilities are also available and the
following cards are accepted for payment: Mastercard/Visa

CANCELLATION No refunds will be made unless a written request for
cancellations received prior to April 1 st 1991. All refunds are
subject to a 10% processing fee. Substitutions will be accepted at any
stay.

ACCOMODATION Hotel accomodation at preferential rates for delegates has
been arranged at Mercure Marseille  Centre 1. rue Neuve Saint-Martin,
and  Captitainerie des Galeres 46, rue Sainte (Both downtown, close to
underground). Hotel reservation and one night deposit must be received
before March 15, 1991.


----------------------------------------------------

Andreas Hohl                 ah@ztivax.siemens.com
ZFE IS EA Ref, SIEMENS AG    tel: (+49) 89-636-41895
Otto-Hahn-Ring 6             fax: (+49) 89-636-44950
8000 Munich 83
FRG

----------------------------------------------------

dettmer@jupiter.ls1.informatik.uni-dortmund.de
phone: +49-231 755 4825, FAX: +49-231 755 2386
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germany