J.Gill.Watt.II@dartmouth.edu (J. Gill Watt II) (02/20/91)
howdy, At the moment, we write VHDL models for parts, compile them and then test them by simulating ( WorkVIEW ViewSIM ) the part. This is very slow and tedious. I was wondering if someone made a VHDL source level debugger that we could use to verify that the code was functioning properly before trying to simulate the part. I am more interested in something in the public domain (i.e. free), but would also like information on commercial packages. Does such a beast exist or am I just dreaming? Thank you. -Gill /***************************************************************** Thayer School of Engineering gill.watt@dartmouth.edu *****************************************************************/