dettmer@jupiter.informatik.uni-dortmund.de (Thomas Dettmer) (02/28/91)
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dettmer@jupiter.informatik.uni-dortmund.de (Thomas Dettmer)
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Last edited: February 20, 1991 (Thanks for all corrections)
Corrections and suggestions are appreciated.
This product list is still incomplete - please help to update it.
This list is without any guarantee to be complete or correct. It is included
to enable contacts to vendors. It does not contain version, quality or price
information. (Please accept, that actually this information changes to fast
-to much work to keep such information up to date, but if there is a
volunteer willing to take this part...:-). Possibly some more information
will be added later. (state information unknown means not to be sure whether
a product is on the market or not)
There is actually no Public Domain stuff known. Most vendors offer special
prices for universities.
********************* Special products **********************************
VHDL Validation Suite Oct 15th, 1990
VHDL VALIDATION SUITE RELEASE ANNOUNCEMENT
The VHDL Validation Suite, which was developed at Va. Tech
with funding provided by CAD Language Systems Inc.,
Daisy/Cadnetix, Genrad, MCC, Silicon Compiler Systems,
Vantage Analysis, and Zycad is now ready for public release.
The suite contains 2295 tests which cover 100% of the 1865
test points defined for the VHDL Language Reference Manual.
The suite is free to universities. Companies and govern-
mental agencies are required to pay a fee of $2000 for the
suite. The funds from these fees will be deposited in the
VHDL Suite Foundation account and will be used to maintain
and improve the suite.
The suite is written in: 1) TAR format on either VAX TK 50
or Sun/Appollo cartridges, or 2) DEC VMS BACKUP format on
TK50 cartridges. To obtain a copy of the suite send :1) ei-
ther a TK 50 (specify whether you want TAR or BACKUP format)
or Sun/Appollo cartridge and 2) a check (not required for
universities) for $2000, made out to VHDL Suite, to:
Professor J. R. Armstrong
Bradley Department of Electrical Engineering
Virginia Tech
Blacksburg, VA. 24061
If you have questions, contact Dr. Armstrong at 703-231-4723
(phone), 703-231-3362 (FAX) or by email sent to
JRA@VTVM1.BITNET.
Proposed IEEE VHDL Standard Logic System: available via anonymous ftp
from bears.ucsb.edu The directory is pub/VHDL, logic_system.tar.Z
******************* Companies and their products ************************
Ascent Technology, Inc.
2075 North Capitol Avenue, Suite C
San Jose, CA 95132
phone: (408) 945-6635, fax: (408) 946-0922
contact: Rindert Schutten
MetaView : basic design environment to be customized
VHDL/DA : Design Assistant (VHDL/DA) : MetaView based environment
for design management, structure editing, browsing, state
machine editing, architecture editing source code
transformation ( for synthesis )
state : Release 1 announced for April 91
CAD Language Systems, Inc.
USA
15245 Shady Grove Road, Suite 310
Rockville, MD 20850
Phone: (301) 963-5200
ax: (301) 963-1511
Europe:
Rosedale House
Rosedale Road
Richmond, Surrey TW9 2SZ, UK
Phone: +44 81 332 0192, FAX: +44 81 948 8263
VTIP virtual tool integration platform state available
RVCG simulation code generator
Cadence Design Systems, Inc.
Systems Division
Two Lowell Research Ctr. Dr.
Lowell, MA 01852-4995
FAX 508-441-1109
OR
555 River Oaks Pkwy.
San Jose, Calif. 95134
Eileen Elam (Public relations representative)
(408) 943-1234
Germany:
Mr. Grothe
phone: 02236 68051
Vdoc Verilog to VHDL translator
VHDL-XL simulator
Computer General Electronic Design Ltd.
(was Praxis Electronic Design)
Contact: Jeremy Goulding, Sales Manager
Computer General Electronic Design Ltd
The New Church
Henry Street
Bath
BA1 1JR
U.K.
phone:+44 225 482744 Fax:+44 225 442751
e-mail:jwg@cged.co.uk
ELLA -> VHDL translator
VHDL synthesis products
Dazix
700E Middlefield Road.
Mountain View, Calif. 94030
I-logix
22 Third Av.
Burlington, MA 01803
Tel. 617 272-8090
Fax. 617 272-8035
Express VHDL: "express and analyze behavioral models graphically"
Intermetrics
733 Concord Ave.
Cambridge, MA 02 138
OR
Suite 415
4733 Bethesda Ave.
Bethesda, MD 20814
phone: (617)661-1840 FAX: (617) 868-2843
email: cms@inmet.inmet.com (C. M. Schmitz)
VHDL Design Environment simulation system SUN/DEC
University Program
ITD
Institute for Technology Development
Advanced MicroElectronics Division
1 Research Blvd. Suite 205
Starkville, Ms. 39759
contact: Scott Calhoun (VHDL modeling group)
phone: (601)-325-8356, email: jscott@itd.msstate.edu
associated with Mississippi State in Starkville, Miss.
package of basic gates, conforms to the preliminary standards under
consideration by the EIA and the modeling standards committee of the IEEE
DASS.
not PD, but available for a copying charge
Logic Automation
Farley Hall
London Road
Bracknell, Berks RG12 5EU, UNITED KINGDOM
phone: +44 344 863230, FAX +44 344 863990
library of models,
MCC
3500 West Balcones Center Dr.
Austin, Texas 78759
USA
Phone: +1 (512) 338 3794
simulator
Model Technology Inc.
15455 N. W. Greenbrier Parkway, Suite 210
Beaverton, OR 97006 USA
Phone: +1 (503) 690-6838, FAX: +1 (503) 690-2093,
BBS: +1 (503) 690-0635
V-System/PC PC based simulator state: available
windows based version announced for 12'90
Mentor Graphics
8500 S.W. Creekside Pl
Beaverton, OR 97005-7191
contact: John Kregel
phone: 503-626-1327, FAX 503-626-1268
2045 Hamilton Ave
San Jose, CA 95125-6199
Phone: 408-371-2900, FAX 408-559-4916
Germany:
Duesseldorf,
Herr Feek
phone: 0211/591011
VHDL Vision/Mentor System 1076 simulation, synthesis, state unknown
Pittsburgh University of [PD/SW?]
Prof. Steven Levitan,
Dept. of Electrical Engineering
348 Benedum Engineering Hall
Univ. of Pitsburgh, 15261
email: vhdl@ee.pitt.edu
see anonymous ftp: ee.pitt.edu (130.49.15.1) in pub/vhdl-info for files
README, letter.txt, license.PS, assurance.PS ...
not public domain, but 150$
analyzer/simulator and sources
Silvar Lisco
Silc Technologies Inc.
Swedish Institute of Microelectronics
VHDL CAD tools
Box 1084
S-164 21 Kista -SWEDEN-
contact: Mart Altmae
phone: +46 8-752 1000 FAX: +46 8-750 8056
email: vhdl@inmic.se, ftp: ftp.inmic.se (130.237.214.90)
MINT multi-level interactive simulation system
Synopsys/ZyCad
Synopsys Inc.:
adress will change soon, they are planning to move)
1098 Alta Av.
Mountain View, CA 94043
Tel. 415 962-5000
Fax. 415 965-8637
England
First Base
Gilette Way
Reading, RG2 OBP
John Miles
Germany
phone: 089/65103101 FAX 089/65103103
Zycad:
1380 Willow Road
Menlo Park, CA 94025
System VHDL simulator/editor
Valid
2820 Orchard Pkwy.
San Jose, Calif. 95134
Germany:
Muenchen,
phone: 089/710050
compiler, simulator
Now sells Intermetrics tools
Vantage Analysis Systems, Inc
USA:
42808 Christy Street, Suite 200
Fremont, CA 94538
phone: (415) 659-0901 fax: (415) 659-0129
contact: John Willey
Europe:
Graham Shenton Associates
Windmill Hill
Whitehill Way, Swindon
Wiltshire SN5 9YZ
UNITED KINGDOM
phone: 011-44-793-875327
fax: 011-44-793-875328
Japan:
Okura & Co, Ltd
3-6 Ginza, 2 chome
Chuo-ku, Tokyo 104
JAPAN
phone: 011-81-3-566-6000
fax: 011-81-3-563-5447
Vantage Spreadsheet, Debug 1076/VHDL simulator, analyzer, debugger
production quality products available since early 1988
Viewlogic
313 Boston Post Rd. West
Marlboro, MA 01752
phone: 508/480-0881, FAX: 508/480-0882, TELEX 174242
ViewSim/SD: subset simulator (next release full VHDL-1076)
VHDL-Designer: synthesis to gate level
ViewGen: schematic drawing synthesis
Export.1076: Automatic VHDL model generation (from which input?)
Vista Technologies, Inc.
USA:
1100 Woodfield Road, Suite 108
Schaumburg, IL 60173-5121
phone: (708) 706-9300, fax: (708) 706-9317
contact: David Jakopac
email: dave@vistatech.com
Japan:
Marubeni Hytech Corp.
Marubeni Hytech Bldg.
20-22, Koishikawa 4-Chome
Bunkyo-ku, Tokyo 112
JAPAN
phone: 81-3-3817-4871, fax: 81-3-3817-4880
contact: Ken Sakamaki
The VHDL Developer: VHDL model development environment. Includes
Language Assistant for design entry and checking,
Source Code Library Manager for design reuse,
over 5000 lines of VHDL examples, and EDIF to VHDL
translator.
The VHDL Developer Plus: Same as The VHDL Developer plus Model Creator
for creating VHDL source from function- and state-
machine-tables. Can generate code campatible for
synthesis.
ZyCad s. Synopsis
dettmer@jupiter.ls1.informatik.uni-dortmund.de
phone: +49-231 755 4825, FAX: +49-231 755 2386
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germany