[comp.lang.vhdl] VHDL and System Level Simulation

jenn@laas.laas.fr (Eric Jenn) (03/26/91)

This will probably looks like a dumb question, but ...

I'm interested by the VHDL language in the framework of system level
simulation. By "system level", I mean  tasks scheduling,  synchronization and
communication between tasks  etc...
 Of course, there are many simulation languages specialized in system level
simulation (GPSS, SIMSCRIPT, SES, CADAS etc...), but most of them are unable to
model low level (gate or RTL)  behaviors easily .
Therefore, choosing one of these languages is a choice that limits ***  a
priori *** the depth (and therefore  the accuracy) of our analysis.
From this point of vue, VHDL seems to be a good choice IFF it provides the
features able to model (more or less easily) the kind of mechanisms we meet in
system level simulation.
So the real question is :
"is VHDL  sufficiently powerful to be a hardware description language AND a
system level simulation language ?"
Any advice or information ?
Thanks a lot ...
Eric

jukka@tk4.oulu.fi (Jukka A. Lahti) (03/27/91)

In article <5508@laas.laas.fr> jenn@laas.laas.fr (Eric Jenn) writes:

>   So the real question is :
>   "is VHDL  sufficiently powerful to be a hardware description language AND a
>   system level simulation language ?"

In my experience, it is. It has all the power you need, if you just
have the patience to write all that code. We have been using VHDL for
high level system modelling for some time, and come to the conclusion
that you definitely need a graphical method (with well defined
semantics) and tool to generate the VHDL models for you. 

We have developed some tools that generate behavioural
VHDL code from graphical Structured Analysis (SA) data-flow and 
state-transition diagrams. I think this is the way to go, if you
don't want to spend all your time writing port- and component
declarations etc.

	- jukka



 
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Jukka Lahti	(jukka@steks.oulu.fi)            Phone:   +358-81-352756
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