<WOOA@QUCDN.QueensU.CA> (03/29/91)
Eric Jenn (jenn@laas.laas.fr) writes: > So the real question is : > "is VHDL sufficiently powerful to be a hardware description language AND a > system level simulation language ?" Jukka Lahki (jukka@tk4.oulu.fi) replied: > In my experience, it is ... you definitely need a graphical method ... I agree with Mr. Lahti in that a graphical interface is the preferred entry mode into VHDL. But I would say from my work that VHDL is not powerful enough to simulate high level modelling paradigms. I have tried to translate Petri nets and statecharts (developed by David Harel) into VHDL and found it too restrictive. For instance, Petri nets are intrinsically non-deterministic and VHDL cannot simulate random ordering of processes. VHDL also lacks complete process control need to stop, suspend, restart processes, a feature required by statecharts. I would be interested to know if anyone else is working on high level modelling in VHDL. Thanks in advance, Arthur Woo Queen's University Kingston, Ontario, Canada woo@eleceng.ee.queensu.ca
jab0396@cec2.wustl.edu (John A. Breen) (03/29/91)
In article <91087.160350WOOA@QUCDN.QueensU.CA> <WOOA@QUCDN.QueensU.CA> writes: >Eric Jenn (jenn@laas.laas.fr) writes: > >> So the real question is : >> "is VHDL sufficiently powerful to be a hardware description language AND a >> system level simulation language ?" > >Jukka Lahki (jukka@tk4.oulu.fi) replied: > >> In my experience, it is ... you definitely need a graphical method ... > >[...] I would say from my work that VHDL is not >powerful enough to simulate high level modelling paradigms. > >I would be interested to know if anyone else is working on high level >modelling in VHDL. I've looked at this problem quite a bit myself. My biggest problem with using VHDL for high-level modeling is that the only communication path between processes is signals. As Mr. Lahki said, you can usually do it if you want to write all of the necessary code, but it's not fun. I would really like to see a high-level communication "object" in VHDL that would take care of all of the overhead that signals require. BTW, I believe I-Logix (sp?) has a tool to translate statecharts into VHDL. ----- John A. Breen | johnb@hobbes.mdc.com McDonnell Douglas Missile Systems Co. | jab0396@cec1.wustl.edu (forwarded ^) Tel: (314)234-4341
vahid@vesta.ics.uci.edu (Frank Vahid) (03/30/91)
>I agree with Mr. Lahti in that a graphical interface is the preferred >entry mode into VHDL. But I would say from my work that VHDL is not >powerful enough to simulate high level modelling paradigms. I have >tried to translate Petri nets and statecharts (developed by David Harel) >into VHDL and found it too restrictive. For instance, Petri nets are >intrinsically non-deterministic and VHDL cannot simulate random ordering >of processes. VHDL also lacks complete process control need to stop, suspend, >restart processes, a feature required by statecharts. I'm not exactly sure of the problems encountered with your StateCharts translation, but I would refer you to a paper entitled "Translating System Specifications to VHDL" which appeared in this year's EDAC Procededings (European Design Automation Conference), dealing with translating languages which are variants of StateCharts to VHDL. I think that a solution to the issue of complete process control is shown. Many other translation problems and solutions are also covered. Frank (vahid@ics.uci.edu)
davidb@inmet.inmet.com (04/02/91)
/* Written 4:03 pm Mar 28, 1991 by WOOA@QUCDN.QueensU.CA */ >For instance, Petri nets are intrinsically non-deterministic and VHDL >cannot simulate random ordering of processes. VHDL also lacks >complete process control need to stop, suspend, restart processes, a >feature required by statecharts. Work at the University of Virginia (under Dr. Jim Ayler) on what they call "Uninterpreted Modeling" tends to negate this conclusion. Their models are similar to Petri nets, although they have some different features. Stoping, suspending, and restarting processes is a matter of having VHDL processes include the logic to wait and re-start as necessary, using the appropriate wait statements. I think the question here is not one of intrinsic power --- after all, VHDL can simulate a Turing machine. The question is one of convenience and ease of use. In many ways VHDL is constructed to facilitate design in the conceptual frame of hardware design. The question is how much one must "bend" his thinking to accomodate systems description to the conceptual frame of VHDL. I have heard varying opinions on this question. The most successful attempts have been similar to the efforts at Virginia --- put a lot of effort into some high level systems models, then concentrate on using the structural aspects of VHDL to instantiate these models; this is a lot closer to the intuitive systems models (especially with a graphics front end, much as I hate the things). Dave Barton barton@i2wash.com
steve@titan.tsd.arlut.utexas.edu (Steve Glicker) (04/04/91)
I am sorry I missed the first part of this discussion because I am very interested in how VHDL might be used to describe high level-system designs. I did see the posting shown below. I would appreciate any references to papers or other leads on work related this topic. If there is interest I will post a summary of my findings. vahid@vesta.ics.uci.edu (Frank Vahid) writes: > I'm not exactly sure of the problems encountered with your StateCharts > translation, but I would refer you to a paper entitled "Translating > System Specifications to VHDL" which appeared in this year's EDAC > Procededings (European Design Automation Conference), dealing with > translating languages which are variants of StateCharts to VHDL. In article <381900013@inmet> davidb@inmet.inmet.com writes: > Work at the University of Virginia (under Dr. Jim Ayler) on what they > call "Uninterpreted Modeling" tends to ... [convey a position on systems modeling with VHDL] > ... The most successful attempts have > been similar to the efforts at Virginia --- put a lot of effort into > some high level systems models, then concentrate on using the > structural aspects of VHDL to instantiate these models; this is a lot > closer to the intuitive systems models ... -- Steve Glicker Applied Research Laboratories The University of Texas at Austin (steve@titan.tsd.arlut.utexas.edu)