bcg@mongoose.harris.com (Bruce Grugett) (04/09/91)
I would appreciate comments from experienced VHDL users on how to estimate the effort required in writing VHDL behavioral models. The models I have in mind would be detailed enough to provide the correct function at the module I/O pins so that tests written for the behavioral model could also be run on the structural VHDL model for the same module to be written later. For example, how much effort would be required to write a model for a module with the following characteristics? 200K gates of logic including a 1750 cpu and 5 ASICs, several memories and some buffers. Also, how should timing and set-up and hold checks be included in the behavioral model? thanks, Bruce Grugett Harris GASD 407-727-5017
drc@coelho (David R. Coelho) (04/16/91)
> estimate the effort required in writing VHDL behavioral models. The > models I have in mind would be detailed enough to provide the > correct function at the module I/O pins so that tests written for the > behavioral model could also be run on the structural VHDL model for > the same module to be written later. A rough rule of thumb goes as follows: ssi, msi (<100 gates equiv): 1 man-day lsi (<1000 gate equiv): 1 man-week vlsi (<10,000 gate equiv): 1 man-month big vlsi (10,000+ gate equiv): up to 1 man-year Past experience modelling the 68000 using the Helix language resulted in a 1 man-year effort amounting to roughly 15,000 lines of code. Helix is very similar to VHDL, and I would expect a similar result in effort and code in VHDL. > Also, how should timing and set-up and hold checks be included in > the behavioral model? Your best bet is to use the VHDL "assertion" statement to establish timing conditions which must be met.