kevin@cheetah.inmos.co.uk (Kevin Cameron) (05/13/91)
When thinking about modelling bi-directional devices like pass transistors and transmission gates for CMOS VLSI circuits, it struck me that VHDL does not have a mechanism for identifying the driver responsible for an event. If the models for such devices could identify that they had previously scheduled the events which activated them then it would be possible to write simpler models for them. What I had in mind was a signal attribute (e.g. 'DRIVER) which would be "true" in the in the process(es) responsible for signal being active in a particular cycle, and "false" in processes which did not schedule any transactions for that cycle. I hope this is a suitable place to discuss such issues - if not where? ------------------------------------------------------------------------------- Kevin Cameron INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK
kgg@cs.ed.ac.uk (Kees Goossens) (05/14/91)
In article <16017@ganymede.inmos.co.uk> kevin@cheetah.inmos.co.uk (Kevin Cameron) writes: >When thinking about modelling bi-directional devices like pass transistors >and transmission gates for CMOS VLSI circuits, it struck me that VHDL does >not have a mechanism for identifying the driver responsible for an event. >If the models for such devices could identify that they had previously >scheduled the events which activated them then it would be possible to >write simpler models for them. > >What I had in mind was a signal attribute (e.g. 'DRIVER) which would be "true" >in the process(es) responsible for signal being active in a particular >cycle, and "false" in processes which did not schedule any transactions for >that cycle. Naive question: What would the use be of such a construct? It could be useful for debugging, but what would be the intuition behind the construct in terms of hardware? How would you simplify the model for transistor level? As I understand the previous paragraphs, it would mean writing a VHDL program, and then, using the 'DRIVER attribute determine which drivers have been used in the computation of the behaviour of the circuit. Those drivers not fires can be deleted. Is that correct? If this understanding is correct, mustn't you do an exhaustive simulation to determine redundant drivers? I have the impression that VHDL's bi-directional features are used mainly as very high level buses or as very low level bidirectional wires (as above). Am I wrong or is there anything in between? Disclaimer: I am not a hardware designer, but am interested in VHDL from a (hardware Description) Language point of view. I would be grateful if someone could post a transistor level description of a NAND gate (say) using more than one signal strength, overpowering and stored charge on the wires, for example? Is VHDL used to model circuits as such a low level, or are specialised simulators like MOSSIM (not detailed enough?) or SPICE (too detailed?) used? >I hope this is a suitable place to discuss such issues - if not where? If this isn't the right place, please let me know too... >Kevin Cameron INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK Kees -- Kees Goossens Keep in Touch with the Dutch: LFCS, Dept. of Computer Science JANET: kgg@uk.ac.ed.lfcs University of Edinburgh, Scotland UUCP: ..!mcsun!ukc!lfcs!kgg Wiskunde is bouwen in de geest. --- Luitzen Egbertus Jan Brouwer.
kevin@cheetah.inmos.co.uk (Kevin Cameron) (05/16/91)
The 'DRIVER suggestion was aimed at modelling CMOS/nMOS pass transistor circuits
when using simple logic types (e.g. MVL4/7). Models for these devices would
typically pass values from one signal (A) to another (B) with a fixed delay. If
there are other processes driving the signal B then the pass transistor model
needs to be able to identify whether the events on B are ones it scheduled - since
these should not be passed back to A. I don't think this can be done without
a more complex logic type at the moment.
Further Suggestion:
Attributes could also be introduced to indicate how many drivers there are for a
signal and how many are active in any cycle e.g.:
B'DRIVERS -- The total number of drivers driving B.
B'ACTIVE_DRIVERS -- The total number of drivers active in this simulation
cycle.
This sort of information is usually stored by VHDL simulators - it just needs a
method for accessing it.
The aim of these suggestions is to enable complex models to be developed for
low level devices (for pass transitor circuits etc.), but using simple logic
types compatible with the simple models which form the bulk of any large
(silicon) design.
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Kevin Cameron INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK
Tel: (UK) 0454 616 616 x364, Fax: 617 910