[comp.lang.vhdl] Naive question

marshall@manse.cs.man.ac.uk (Robert Marshall) (05/09/91)

Can anyone tell me of the rationale behind the `component_configuration's being
in the declarative part of the architecture?

What is the statement declaring, the instantiation label? To my way of thinking
the configuration is providing associations between previously declared
`entities'(not the VHDL keyword!) that will be resolved at elaboration time
rather than a declaration.
The motivation behind the question is:
does the configuration apply to the component or to the instantiations?
Yes I know it applies to both! but in your conceptual model of the design is
the following:
component x port(...) end component;
for all : x use entity a;
...
x1 : x...;
x2 : x...;
x3 : x...;
x4 : x...;

just a shorthand for:
----

for x1 : x use entity a;
for x2 : x use entity a;
for x3 : x use entity a;
for x4 : x use entity a;
 or is it saying something about the `virtual design unit' declared by the
component? In other words does the component configuration logically belong to
the component declaration or the individual instantiations?

Robert
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davidb@inmet.inmet.com (05/16/91)

/* Written  7:54 am  May  9, 1991 by marshall@manse.cs.man.ac.uk */

>Can anyone tell me of the rationale behind the component
>configuration's being in the declarative part of the architecture?

First of all, what follows is my opinion: I don't think this question
was even addressed in the original 7.2 rationale, and I am pretty sure
that it was not addressed in the IEEE rationale (since it was not a
difference between 7.2 and IEEE).

The configuration specification is in the declarative part because it
is a binding mechanism (thus the name, "binding_indication" for the
mapping portion of the construct).  Declaration is a two step process:
creating the name of the mumble (where mumble includes objects, types,
components, labels, and anything else that needs to be declared) and
binding the mumble to the appropriate "already known" concept: storage
location for object, previously known types for types, etc.  For
components, this two step process is done in two steps rather than
one: creating the name of the component, then binding it to the
appropriate library entity-architecture pair.  The component
declaration does the former, and the configuration specification does
the latter.

>What is the statement declaring, the instantiation label? 

As stated above, the configuration specification is a binding.  It
creates no new name; thus, does not fully "declare" anything.

>To my way of thinking the configuration is providing associations
>between previously declared `entities'(not the VHDL keyword!) that
>will be resolved at elaboration time rather than a declaration.  The
>motivation behind the question is: does the configuration apply to the
>component or to the instantiations?  Yes I know it applies to both!
>but in your conceptual model of the design is the following:

>component x port(...) end component;
>for all : x use entity a;
>...
>x1 : x...;
>x2 : x...;
>x3 : x...;
>x4 : x...;

>just a shorthand for:
----

>for x1 : x use entity a;
>for x2 : x use entity a;
>for x3 : x use entity a;
>for x4 : x use entity a;

>or is it saying something about the `virtual design unit' declared by
>the component? In other words does the component configuration
>logically belong to the component declaration or the individual
>instantiations?

The binding indication (whether in a configuration specification or a
configuration declaration) established the binding between the
component declaration and the library entity/architecture on an
instantiation basis.  I don't know what a "virtual design unit" is;
the two forms you give above are equivalent in their action.

I hope this helps.  I again emphasize that this is my opinion, and not
a reporting of official doctrine.

						Dave Barton
						barton@i2wash.com