wdb@vhdl (W. Billowitch) (05/23/91)
Dear VHDL Developer :
Over the past year the EIA and IEEE have worked individually toward
standard packages for VHDL model developers. Of particular interest
are the EIA's BASICDEFS package and the IEEE's Std_Logic_1164 package.
Now is the time for the two packages to merge into one for the benefit
of the user community.
In agreement with the EIA's representative Len Finegold, the following
modifications will be made to the EIA's BASICDEF's package to allow
models to be written such that they are port type compatible using either
the EIA set of packages or the IEEE's package set.
We hope that you will look upon this merger of activities in the standard
logic system package area in the same positive light as do the authors.
Many thanks to all of those who contributed to the development of the
standards and to all of the CAE vendors who are currently supporting
this effort.
Sincerely,
-------------------------------------- ---------------------------------
William D. Billowitch Len Finegold
Chairman Chairman
IEEE VHDL Model Standards Group EIA Model Standards Committee
vhdl!wdb@uunet.uu.net
The Modifications to the EIA BASICDEFS package follows....
-- --------------------------------------------------------------------
--
-- File name : basicdefs.mod.vhdl
-- Title : EIA Basicdefs package modified to be compatible to the
-- : IEEE 9-state logic system.
-- Library : STD
-- Purpose : The modifications suggested here will make the EIA and
-- : IEEE Packages compatible and allow designers to use
-- : either package freely without requiring the use
-- : of type conversion functions.
-- :
-- Notes :
-- :
-- --------------------------------------------------------------------
-- Modification History :
-- --------------------------------------------------------------------
-- Version No:| Author:| Mod. Date:| Changes Made:
-- v2.000 | wdb | 9/13/90 | Original EIA package developed
-- | by Dave Cantwell ( Hughes )
-- | and Len Finegold ( General Dynamics )
-- v3.000 | wdb | 5/17/91 | Modifications to provide compatibility
-- --------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_logic_1164.all; -- reference to IEEE package
Package BASICDEFS is
-- establish "std_ulogic" as the base type
SUBTYPE logic_mv is std_ulogic range 'U' to 'H'; -- ( 'U','X','0','1','Z','W','L','H');
TYPE logic_vector_mv is array (natural range <> ) of logic_mv;
TYPE logic_mv_table is array (logic_mv, logic_mv ) of logic_mv;
-------------------------------------------------------------------------
-- CONSTANT DECLARATIONS ...
-------------------------------------------------------------------------
constant UNINIT : logic_mv := 'U';
constant UNKNOWN : logic_mv := 'X';
constant ZERO : logic_mv := '0';
constant ONE : logic_mv := '1';
constant HIGHZ : logic_mv := 'Z';
constant RES_UNKNOWN : logic_mv := 'W';
constant RES_LOW : logic_mv := 'L';
constant RES_HIGH : logic_mv := 'H';
constant DONT_CARE : std_ulogic := '-'; -- additional constant for synthesis
--- Overloaded operators, bus resolutions remain...All other functions
will be moved to a separate package.
end BASICDEFS;