rayv@revenge.oakhill.uucp (Ray Voith) (05/17/91)
Hopefully this will not appear twice - I previously posted it to the wrong news category. ------------------------------------------------- I am looking at the EIA/IEEE logic modeling packages. I am a little confused, since I thought that there would be only one resultant package that both agreed upon. I have two apparently different VHDL packages: One from Len Finegold (EIA) and one from Victor Berman/W. Billowitch (IEEE). They are different. I have not examined them in great detail, since I am not sure whether the intent is to have only one package eventually. I am wondering if anyone out there has an answer to the questions: - is one a subset of the other? - are they compatible but different internally? - what supporting stuff is safe to use with both? The point is that if they are not the same, and have different supporting packages (e.g. TIME_FUNCS), then it is unclear which one is the industry standard. It is also unclear which supporting code will work with which package. Thanks for any help on this. I am sending a copy of this note to Finegold and Billowitch. Ray Voith rayv@revenge.sps.mot.com 512-891-2265
berman@pebbles.cadence (Victor Berman; x6276) (05/25/91)
The IEEE package is currently the one being looked at as the standard. The EIA has agreed to track the IEEE package and divide out those functions which are not in common into a separate package which will be supplied as a sort of recommended tool kit but not as part of the required standard. The issue of the don't care state which is currently in the IEEE but not in EIA is still not entirely resolved. The EIA feels that this state is not appropriate for actual parts models and may stick with a sub-type excluding this state. Victor Berman berman@cadence.com