janick@bcrkd13.bnr.ca (Janick Bergeron) (06/15/91)
We ran accross what we, at first, thought was a bug in the toolset we are
using. Here's an example:
entity E is
end E;
architecture A of E is
subtype T is Bit_Vector(3 downto 0);
signal S1 : T := "1111";
signal S2 : Bit_Vector(7 downto 0) := "00000000";
begin
S2 <= S1 & "1111";
end A;
A constraint error is issued for the concatenation operation. The LRM states
that "The left bound of this results is the left bound of the left operand,
(...). The direction of the result is the direction of the left operand, (...)"
which means that the resulting bit vector has an index range of 3 downto -4.
This clearly violates the constraint on the index of the predefined BIT_VECTOR
type (i.e. NATURAL range <>).
My question is: why set the range based on the left operand ? That would make
sense if you could index the result of the expression directly without
assigning it to an intermediate variable e.g. (S1 & "1111")(2 downto 1)
but this is not a valid VHDL indexed_name anyway!
Why not keep the direction of the left operand but set the lowest bound
to '0' ??
In the meantime, I use "S2 <= S1(3) & S1(2 downto 0) & "1111"" as work-around.
--
Janick Bergeron Bell-Northern Research, Ltd Ph.: (613) 763-5457
VHDL Tools P.O. Box 3511, Station C, Stop 049 Fax: (613) 763-7241
Ottawa, Ontario, Canada, K1Y 4H7 Flame: 1-800-DEV-NULL
janick@bnr.ca library disclaimer; use disclaimer.all;