dltaylor@cns.SanDiego.NCR.COM (Dan Taylor) (04/26/91)
68040s have single bus, too, though the internal I/D split is nice. Nearly all commercial bus architectures are only single ported, even if you can run I on VSB and D on VME. Remember Motorola is (was?) trying to sell the 88K, with separate cache/MMU for I and D. I'll wager my $0.02 that if the 88K market doesn't pick up, soon, that we'll see a 680X0 with separate I and D (it's mostly a package problem, since the internal paths are already disjoint). That won't be the real speed demon, though. You could use the extra pinouts to do 128-bit data transfers to the internal cache lines. Since the I and D are already separate at the caches, you can still use a unified memory bus model, but see a 2-4 times increase in performance without raising the clock rate (assuming that the CPU is memory I/O bound). You can bump FP performace by gating the FP accesses through their own 64-bit data paths. The platform for all this would be a FutureBus system, since it can support 128-bit (256, too) data paths. None of this is news to Motorola, it's just that they only have so many designers, and they've got a few other products, like the 96000 family to do, too. 'Course, I'd like to have an Amiga X000, with 128-bit RAM for the CPU and Custom Chips (for $2500, natch). Gee, Dave, 1992? Dan Taylor /* My opinions, not NCR's. */