barrett@jhunix.HCF.JHU.EDU (Dan Barrett) (04/23/91)
In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: >>The 1+ has a few MIPS on the 040. >WRONG. The Sparc 1+ is rated 15mips and so is the 68040. I was under the impression that RISC MIPS and CISC MIPS are not directly comparable like this. Dan //////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ | Dan Barrett, Department of Computer Science Johns Hopkins University | | INTERNET: barrett@cs.jhu.edu | | | COMPUSERVE: >internet:barrett@cs.jhu.edu | UUCP: barrett@jhunix.UUCP | \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\/////////////////////////////////////
melling@cs.psu.edu (Michael D Mellinger) (04/23/91)
In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes: In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: >>The 1+ has a few MIPS on the 040. >WRONG. The Sparc 1+ is rated 15mips and so is the 68040. I was under the impression that RISC MIPS and CISC MIPS are not directly comparable like this. Actually, the best way to compare performance is with SPECmarks. CISC instructions in general do more than RISC instructions. Therefore a 15 mip CISC(the NeXT) is probably a little faster than a 15 mip RISC(Sparc 1+). Although, I did have an instructor that said the difference in the amount of work done by a CISC instructions in comparison to RISC instruction is overemphasized. To sum it it, look at the SPECmarks. Mips are lies. -Mike
ddyer@hubcap.clemson.edu (Doug) (04/23/91)
melling@cs.psu.edu (Michael D Mellinger) writes: >In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes: > In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: > >>The 1+ has a few MIPS on the 040. > >WRONG. The Sparc 1+ is rated 15mips and so is the 68040. > I was under the impression that RISC MIPS and CISC MIPS are not > directly comparable like this. >Actually, the best way to compare performance is with SPECmarks. CISCS Just for everyones record: (off comp.arch) no cache 68040 486 SPARC330 68040 Integer gcc 13.8 13.8 13.8 12.4 espresso 13.4 12.2 11.6 12.8 li 15.5 16.8 11.2 14.9 eqntott 9.8 11.0 12.6 9.7 FP spice2g6 13.1 8.8 11.4 11.8 doduc 8.1 5.8 9.5 7.7 nasa7 12.1 5.8 14.0 11.5 matrix3000 11.5 9.5 14.7 10.8 fpppp 13.4 7.0 13.1 12.1 tomcatv 9.1 4.3 8.2 8.4 Means SPECmark 11.8 8.8 11.8 11.0 Integer 12.9 13.3 12.3 12.3 FP 11.0 6.6 11.6 10.2 All three are at 25mhz with 128k cache Note that SUN SS1+ is only 10.0 specmark (25mhz, 64kb cache) True, RISC has a MUCH higher instruction bandwidth than CISC. Still, in the experimental end, CISC (in the literal sense) is comming back in machines such as RS/6000, and HP cobras. They have a lengthy instruction set where complicated instructions (such as fused multiply-add) are shown to improve performance. I feel that the big loss in traditional CISC is in sticking architectural baggage on every new generation. Nick Trennedick (sp) mentioned that its highly intimidating to chase obscure quirks in the previous generation and have to implement them. Spare the flames against SPECmark and benchmarks. On the other hand, Im no architect expert (FAR cry from architect mongo level), so flame away! Mongo just pawn in chess game of life. Bye, Doug -- Doug Dyer ddyer@hubcap.clemson.edu
dwboyce@acsu.buffalo.edu (Doug Boyce) (04/23/91)
In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes: >In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: >>>The 1+ has a few MIPS on the 040. >>WRONG. The Sparc 1+ is rated 15mips and so is the 68040. > > I was under the impression that RISC MIPS and CISC MIPS are not >directly comparable like this. Another thing is that the 68040 is blurring the line between CISC and RISC. A RISC chip is supposedly one that executes one instruction per clock cycle. The '040 averages 1.3 instructions per, making them more similar than dissimilar (in this specific instance). -- Doug Boyce dwboyce@acsu.buffalo.edu "Speedballs are interesting if you aren't the cannoneer doing the running." "Where's that Lotto ticket, I want a NeXT NoW!"
drtiller@uokmax.ecn.uoknor.edu (Donald Richard Tillery Jr) (04/24/91)
In a message From: dwboyce@acsu.buffalo.edu (Doug Boyce) >In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes: >>In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: >>>>The 1+ has a few MIPS on the 040. >>>WRONG. The Sparc 1+ is rated 15mips and so is the 68040. >> >> I was under the impression that RISC MIPS and CISC MIPS are not >>directly comparable like this. > >Another thing is that the 68040 is blurring the line between CISC and RISC. >A RISC chip is supposedly one that executes one instruction per clock >cycle. The '040 averages 1.3 instructions per, making them more similar >than dissimilar (in this specific instance). > According to Motorola's Technical Data sheet on the MC68040: "o 20 MIP Integer Performance o 3.5 MFLOP Floating-Point Performance o IEEE 754-Compatible FPU o Independent Instruction and Data MMUs o 4K-Byte Physical Instruction Cache and 4K-Byte Physical Data Cache Accessed Simultaneously o 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface o User-Object-Code Compatibility with All Earlier M68000 Microprocessors o Multimaster/Multiprocessor Support via Bus Snooping o Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput o 4-Gbyte Direct Addressing Range o Software Support Including Optimizing C Compiler and UNIX(R) System V Port" Looks like this CISC chip is right in there with all those RISC chips and you don't have to make any allowances like re-writing your code :-) Rick Tillery
melling@cs.psu.edu (Michael D Mellinger) (04/24/91)
In article <1991Apr24.043828.7213@uokmax.ecn.uoknor.edu> drtiller@uokmax.ecn.uoknor.edu (Donald Richard Tillery Jr) writes:
[awesome specs for the 68040 deleted]
Looks like this CISC chip is right in there with all those RISC chips and
you don't have to make any allowances like re-writing your code :-)
Look at the SPECmarks that were posted earlier yesterday. They're
more indicative of the actual performance. By this time next year,
MIPS will have a 50 mip processor that only runs at 25MHz. HP has a
RISC chip in their Snake machines that SPECS at 54. It costs around
$12,000. The 68040 SPECs at around 12 or 13.
The i860 is a RISC chip. Look at its benchmarks sometime.
Also, quit writing your code in assembler. That's not how it's done
anymore. The Amiga doesn't have enough good professional software as
it is. What's going to happen when everyone switches to RISC
chips(NeXT is going to), but Commodore can't because all of the Amiga
software software is written in assembler?
-Mikeswarren@convex.com (Steve Warren) (04/24/91)
In article <aodGmk7x1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: > >In article <1991Apr24.043828.7213@uokmax.ecn.uoknor.edu> drtiller@uokmax.ecn.uoknor.edu (Donald Richard Tillery Jr) writes: > > > [awesome specs for the 68040 deleted] > > Looks like this CISC chip is right in there with all those RISC chips and > you don't have to make any allowances like re-writing your code :-) > > >Look at the SPECmarks that were posted earlier yesterday. They're >more indicative of the actual performance. I saw the SPECmarks numbers. What conclusion are you drawing from them? It looked to me like the 68040 beat the SPARC more than the SPARC beat the 68040. But for the most part they were roughly comparable. In fact, their performance was amazingly similar, considering the disparity in architecture of the two CPUs. This is right in line with the statement above, that "...this CISC chip is right in there with all those RISC chips..." > ... By this time next year, >MIPS will have a 50 mip processor that only runs at 25MHz. OK, but the same argument applies to the R4000 that applies to the 68040, that is, it ain't here 'till it's here. BTW, the R4000 is a 64 bit CPU, so it is not surprising that it can double the performance figures at the same clock rates. I am sure that a "son-of-SPARC" machine in a 64-bit incarnation would come in in the same ballpark, if slightly lower. Ditto for the analogous hot 64-bit CISC machine that would incorporate the kind of design philosophy that was behind the 68040. There is no magic bullet. The same performance enhancing architectural features can be added to most families and the result will be similar performance boosts. It *is* true that the more complex instruction set of the 680X0 family means that it takes more silicon to do it. But no doubt the R4000 will be a really sweet engine. > ... HP has a >RISC chip in their Snake machines that SPECS at 54. It costs around >$12,000. The 68040 SPECs at around 12 or 13. Then HP will probably rule the world in a year or 2. ;^) (emphasis on smily) >The i860 is a RISC chip. Look at its benchmarks sometime. The i860 has a lot of problems, too. The OEMs that are incorporating the i860 into their designs are having problems, from what I understand. >Also, quit writing your code in assembler. That's not how it's done >anymore. The Amiga doesn't have enough good professional software as >it is. Yes sir, anything else, sir? ;^) > What's going to happen when everyone switches to RISC >chips(NeXT is going to), but Commodore can't because all of the Amiga >software software is written in assembler? I believe the rumors of the death of CISC are a little premature. But we'll all see in another year or two. Markets are shaking out big-time this year. > >-Mike _. --Steve ._||__ DISCLAIMER: All opinions are my own. Warren v\ *| ---------------------------------------------- V {uunet,sun}!convex!swarren; swarren@convex.com --
leblanc@eecg.toronto.edu (Marcel LeBlanc) (04/25/91)
swarren@convex.com (Steve Warren) writes: >I saw the SPECmarks numbers. What conclusion are you drawing from them? >It looked to me like the 68040 beat the SPARC more than the SPARC beat the >68040. But for the most part they were roughly comparable. In fact, their >performance was amazingly similar, considering the disparity in architecture >of the two CPUs. This is right in line with the statement above, that >"...this CISC chip is right in there with all those RISC chips..." The statement would be true if it read as "...this CISC chip [the 68040] is right in there with that one RISC chip [SPARC]..." ^^^^^^^^ The simple fact is that the SPARC-1 implementations are providing the WORST performance of any RISC processors, largely due to the shared instruction+data cache (bus, really). Also add to the fact that the 68040 has been available for all of 4 months now, while 25 MHz SPARCs have been available for 2.5 years! Today, SPARCs and R3000As are available in 40 MHz speeds, with newer implementations such as the 3-chip HP PA available at up to 66 MHz. For a 4 month old chip, the 68040 is not farring very well at all with "all those RISC chips...". >--Steve ._||__ DISCLAIMER: All opinions are my own. > Warren v\ *| ---------------------------------------------- Marcel A. LeBlanc -- Electrical Eng. Computer Group, Univ. of Toronto ----------------------------------------------------------------------- leblanc@eecg.toronto.edu else: uunet!utcsri!eecg!leblanc
peter@sugar.hackercorp.com (Peter da Silva) (04/28/91)
Will you guys take the CISC versus RISC flamage elsewhere (like comp.arch.mips. is.better.than.sparc.no.it.isnt)? Anyone who can look at systems and claim that traditional CISC chips have any advantage in a normal workstation is fooling themselves. CISC still has an advantage at the low end, where the memory subsystem isn't fast enough to keep those RISC monsters fed, but that's fading fast. Certainly the A3000 is fast enough to feed a RISC chip, and a RISC co-processor card (not those sluggish transputers... a real RISC like a MIPS or SPARC (or maybe an HP snake :->)) would be killer. The older 2000 and 500 are better off with a 680x0. I would expect a RISC chip on one of them to actually slow things down. CISC also has an advantage in the embedded controller market, where memory constraints limit you to assembly and Forth. At the very high end, with separate data and instruction memory and many-way interleaved data memory, the ability of CISCs to schedule multiple data requests per instruction might give them a bit of an advantage too. There they're competing with superscalar and VLIW, though. But for a workstation, running UNIX, why go with a CISC in a new box? -- Peter da Silva. `-_-' <peter@sugar.hackercorp.com>.
peter@sugar.hackercorp.com (Peter da Silva) (04/28/91)
In article <aodGmk7x1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: > What's going to happen when everyone switches to RISC > chips(NeXT is going to), but Commodore can't because all of the Amiga > software software is written in assembler? Too late for that. -- Peter da Silva. `-_-' <peter@sugar.hackercorp.com>.
peter@sugar.hackercorp.com (Peter da Silva) (04/28/91)
In article <1991Apr24.135141.21417@convex.com> swarren@convex.com (Steve Warren) writes: > I saw the SPECmarks numbers. What conclusion are you drawing from them? > It looked to me like the 68040 beat the SPARC more than the SPARC beat the > 68040. That's like claiming your bicycle is as good as a car because it can keep up with an ailing VW Beetle. The SPARC is at best a mediocre RISC chip. Try comparing it to the 88000 or the MIPS. -- Peter da Silva. `-_-' <peter@sugar.hackercorp.com>.
ddyer@hubcap.clemson.edu (Doug) (04/28/91)
peter@sugar.hackercorp.com (Peter da Silva) writes: >In article <1991Apr24.135141.21417@convex.com> swarren@convex.com (Steve Warren) writes: >> I saw the SPECmarks numbers. What conclusion are you drawing from them? >> It looked to me like the 68040 beat the SPARC more than the SPARC beat the >> 68040. >That's like claiming your bicycle is as good as a car because it can keep up >with an ailing VW Beetle. The SPARC is at best a mediocre RISC chip. Try >comparing it to the 88000 or the MIPS. >-- >Peter da Silva. `-_-' ><peter@sugar.hackercorp.com>. OK! Again, just for the record... (taken from comp.arch) Part of a posting by Michael Slater: -------------------------------------------------------------------- Vendor Moto Moto Intel Sun MIPS Moto IBM Intel Achitecture 68040 68040 486 SPARC R3000 88000 RS/6000 i860 Cache none 128K 128K 128K 128K 128K 64K/8K none Clock (MHz) 25 25 25 25 25 25 25 33 -------------------------------------------------------------------- Integer gcc 12.4 13.8 13.8 13.8 15.5 17.5 17.8 11.5 espresso 12.8 13.4 12.2 11.6 17.7 19.4 20.7 20.0 li 14.9 15.5 16.8 11.2 20.4 20.7 19.8 17.7 ------------------------------------------------------------------- FP spice2g6 11.8 13.1 8.8 11.4 12.1 12.5 27.6 14.8 doduc 7.7 8.1 5.8 9.5 15.9 10.1 27.7 15.6 nasa7 11.5 12.1 5.8 14.0 18.1 15.2 35.5 45.0 matrix300 10.8 11.5 9.5 14.7 13.8 18.4 21.8 21.5 fpppp 12.1 13.4 7.0 13.1 17.8 14.7 54.7 21.8 tomcatv 8.4 9.1 4.3 8.2 13.9 11.6 75.7 34.0 -------------------------------------------------------------------- Means SPECmark 11.0 11.8 8.8 11.8 16.1 15.2 28.9 20.3 Integer 12.3 12.9 13.3 12.3 17.6 18.3 20.2 16.4 FP 10.2 11.0 6.6 11.6 15.1 13.5 36.7 23.4 ------------------------------------------------------------------ SPEC benchmark results for CISC and RISC systems at 25 MHz (except i860 at 33 MHz). All results as published by SPEC, except for 486 and 860 results published by Intel and 68040 results provided by HP. The systems are the HP 425t, HP 425s, an unspecified 486 system, Sun SPARCstation 330, MIPS RC3240, Motorola 8864SP, IBM RS/6000 Model 530, and an 860 PC add-in board with static column DRAM. Cache sizes shown are external (second-level) caches only, except for RS/6000. MIPS and 88K caches are 64K instruction and 64K data. ------------------------------------------------------------------- Michael Slater, Editor and Publisher, Microprocessor Report mslater@cup.portal.com 707/823-4004 fax: 707/823-0504 874 Gravenstein Hwy. So., Suite 14, Sebastopol 95472 -- Doug Dyer ddyer@hubcap.clemson.edu
peter@sugar.hackercorp.com (Peter da Silva) (04/30/91)
In article <1991Apr28.145704.12706@hubcap.clemson.edu> ddyer@hubcap.clemson.edu (Doug) writes: > peter@sugar.hackercorp.com (Peter da Silva) writes: > >In article <1991Apr24.135141.21417@convex.com> swarren@convex.com (Steve Warren) writes: > >That's like claiming your bicycle is as good as a car because it can keep up > >with an ailing VW Beetle. The SPARC is at best a mediocre RISC chip. Try > >comparing it to the 88000 or the MIPS. > OK! Again, just for the record... (taken from comp.arch) Yep. The CISC guys are consistently slower than the RISC guys, and not by just a few percent. And you're not even counting the Snake. -- Peter da Silva. `-_-' <peter@sugar.hackercorp.com>.