ckp@grebyn.com (Checkpoint Technologies) (06/30/91)
In article <1991Jun29.150321.9791@NCoast.ORG> davewt@NCoast.ORG (David Wright) writes: >In article <1991Jun29.005127.17803@grebyn.com> ckp@grebyn.com (Checkpoint Technologies) writes: >>In article <greg.0954@pfloyd.lonestar.org> greg@pfloyd.lonestar.org (Greg Harp) writes: >>>I have always had a bit of a beef with this one. What the *hell* kind of >>>good does 1 parity bit do you? >>It does exactly one bit more good than no bits. :-) > No, actually it is WORSE, at least in the brain-dead way that >IBM clones use it. If you have 1 bit out of 9 for parity, with no >error correction, that means that more than 10% of the time the error >will be in the parity bit itself. Since PC clones are not designed to >have any ECC bits, and the whole parity detection system is >incredibly archaic, a parity error just brings the whole machine to a >halt, even when it is in the parity bit itself. But it was a FAILURE. If the parity bit fails, then your error detection mechanism failed, and it should be reported. > I cetainly call this "less reliable", since you have now added >a "feature" that will cause the computer to seemingly "fail" over 10% >more than it normally would. If a RAM bit fails x times, then adding 10% more RAM bits should cause 10% more failures. Correct. Of course, the same thing happens when you add another bank of expansion RAM chips. > Further, the PC is too brain-dead to even see where the >address is, and whether it is in use. A parity error outside of >active memory should, at the most, pop up a requestor notifying you >it occured, without halting the system at all (oops, PC don't have >multitasking). There's no way to detect a parity failure unless you've just read the word containing the bad bit. By definition this bit is in use, since you used it to detect the failure. Now, with ECC systems there could be "scrubbing" taking place, which means that the memory subsystem walks through memory, independent of the CPU, looking for bad words, correcting them, and writing them back. But I've never heard of a scrubbing system for parity RAM. > I have been working with PC's since the first IBM "PC" (not even XT) >came out, and in ALL THAT TIME, I have only seen 2, thats *TWO* parity >errors. Both of which were over 6 years ago. And they occured on fairly >low-quality RAM boards at that. So what this means is that all PC clone >owners, whether they would want it or not, have been force to buy over >10% more RAM than they need, for a "feature" that was at best only crudely >implemented, and which increases the posibility of false "errors" and MTBF >by over 10%. Great deal there. But parity RAM increases the chance of detecting a failure. Apparently those customers were satisfied that that was a reasonable cost/reliability compromise (or at least, they trusted IBM's opinion that it was a reasonable compromise). > Dave Inmos once had a 256K dynamic RAM chip that contained complete error detection and correction circuitry within it. It's too bad this chip did not succeed in the marketplace. It would make a great option for dealers, if they could insert ECC RAM into *any* computer system. -- Richard Krehbiel, private citizen ckp@grebyn.com (Who needs a fancy .signature?)