uzun@pnet01.cts.com (Roger Uzun) (05/05/91)
[]
I am trying to assemble the compress.asm listing that was posted here,
it was for Macro 68 originally. 2 questions :
1) In the code it has a line saying : IFGT EntryBitsPerHash, some
sort of psuedo-op. What does it mean? Is it conditional assembly?
it also has an ELSE and ENDIF for the IFGT. How do I
translate this section for the Lattice Assembler?
2) Is bhs.s the same as bhi.s followed by beq.s? That is what
I assumed, bhs is not a true 68000 opcode in any case.
That is about it, I am trying to get it working from C, using lattice C 5.10a
If anyone knows about macro 68, and the above anomalies, please let
me know.
-Roger
UUCP: {hplabs!hp-sdd ucsd nosc}!crash!pnet01!uzun
ARPA: crash!pnet01!uzun@nosc.mil
INET: uzun@pnet01.cts.comjcs@crash.cts.com (John Schultz) (05/07/91)
In <9037@crash.cts.com> uzun@pnet01.cts.com (Roger Uzun) writes: >[] >I am trying to assemble the compress.asm listing that was posted here, >it was for Macro 68 originally. 2 questions : >1) In the code it has a line saying : IFGT EntryBitsPerHash, some > sort of psuedo-op. What does it mean? Is it conditional assembly? > it also has an ELSE and ENDIF for the IFGT. How do I > translate this section for the Lattice Assembler? It's a macro. IFGT = if greater than = if greater than zero: true. It is conditional assembly (probably). Otherwise it expands to the appropriate run time instructions. >2) Is bhs.s the same as bhi.s followed by beq.s? That is what > I assumed, bhs is not a true 68000 opcode in any case. bhs = bhis = bcc = branch if higher or same, unsigned, or branch if carry clear. I've used Lattice asm, Devpac-2, CAPE, and Adapt. I don't have Macro68, but it does support the new Motorola Standard syntax, which may lend to confusion. John
mykes@amiga0.SF-Bay.ORG (Mike Schwartz) (05/07/91)
In article <9037@crash.cts.com> uzun@pnet01.cts.com (Roger Uzun) writes: >[] >I am trying to assemble the compress.asm listing that was posted here, >it was for Macro 68 originally. 2 questions : > >1) In the code it has a line saying : IFGT EntryBitsPerHash, some > sort of psuedo-op. What does it mean? Is it conditional assembly? > it also has an ELSE and ENDIF for the IFGT. How do I > translate this section for the Lattice Assembler? > This is conditional assembly. The 'C' equivalent: #if EntryBitsPerHash > 0 ... #endif >2) Is bhs.s the same as bhi.s followed by beq.s? That is what > I assumed, bhs is not a true 68000 opcode in any case. > bhs.s means "branch higher or same" and it IS a true 68000 opcode. It is an unsigned branch while bge is signed. >That is about it, I am trying to get it working from C, using lattice C 5.10a > >If anyone knows about macro 68, and the above anomalies, please let >me know. These are not anomalies, and you should find these "basic" features in any assembler you consider using. They were in the oldest Metacomco assembler available... >-Roger > >UUCP: {hplabs!hp-sdd ucsd nosc}!crash!pnet01!uzun >ARPA: crash!pnet01!uzun@nosc.mil >INET: uzun@pnet01.cts.com -- **************************************************** * I want games that look like Shadow of the Beast * * but play like Leisure Suit Larry. * ****************************************************
ttobler@unislc.uucp (Trent Tobler) (05/09/91)
From article <mykes.2256@amiga0.SF-Bay.ORG>, by mykes@amiga0.SF-Bay.ORG (Mike Schwartz): >>2) Is bhs.s the same as bhi.s followed by beq.s? That is what >> I assumed, bhs is not a true 68000 opcode in any case. >> > > bhs.s means "branch higher or same" and it IS a true 68000 opcode. It > is an unsigned branch while bge is signed. No, it is not a true 68000 opcode. The branching instructions are: Cond. 0000 BRA always 0001 --- used for the BSR instruction 0010 BHI C and Z clear 0011 BLS C or Z set 0100 BCC C clear 0101 BCS C set 0110 BNE Z clear 0111 BEQ Z set 1000 BVC V clear 1001 BVS V set 1010 BPL N clear 1011 BMI N set 1100 BGE N = V (ie both set or both clear) 1101 BLT N != B (ie one is set and one is clear) 1110 BGT Z clear, and N = V 1111 BLE Z set, and N != V > These are not anomalies, and you should find these "basic" features in any > assembler you consider using. They were in the oldest Metacomco assembler > available... So what do the assemblers do? Generate a BHI and BEQ sequence? - Trent Tobler - ttobler@csulx.weber.edu
jlavin@cie.uoregon.edu (Jeff Lavin) (05/10/91)
In article <1991May8.205935.26761@unislc.uucp> ttobler@unislc.uucp (Trent Tobler) writes: >From article <mykes.2256@amiga0.SF-Bay.ORG>, by mykes@amiga0.SF-Bay.ORG (Mike Schwartz): > >>>2) Is bhs.s the same as bhi.s followed by beq.s? That is what >>> I assumed, bhs is not a true 68000 opcode in any case. >>> >> >> bhs.s means "branch higher or same" and it IS a true 68000 opcode. It >> is an unsigned branch while bge is signed. > >No, it is not a true 68000 opcode. The branching instructions are: > >Cond. >0000 BRA always >0001 --- used for the BSR instruction >0010 BHI C and Z clear >0011 BLS C or Z set >0100 BCC C clear >0101 BCS C set >0110 BNE Z clear >0111 BEQ Z set >1000 BVC V clear >1001 BVS V set >1010 BPL N clear >1011 BMI N set >1100 BGE N = V (ie both set or both clear) >1101 BLT N != B (ie one is set and one is clear) >1110 BGT Z clear, and N = V >1111 BLE Z set, and N != V > >> These are not anomalies, and you should find these "basic" features in any >> assembler you consider using. They were in the oldest Metacomco assembler >> available... > >So what do the assemblers do? Generate a BHI and BEQ sequence? > >- > Trent Tobler - ttobler@csulx.weber.edu Simple, BHS is equivalent to BCC (unsigned). Because of the user configuration file, Macro68 allows you to rename all directives and opcodes. This allows both a large amount of compatibility with other assemblers, and a lot of flexibility. Some folks have reported renaming the signed branches in order to make it easier for them to remember which are signed and which are unsigned. Whatever you call it, on the 68K family of processors, BCC is equivalent to an unsigned Branch Higher or Same, and BCS is equivalent to an unsigned Branch Lower. The Puzzle Factory, Inc. | Jeff Lavin -- jlavin@cie.uoregon.edu Veneta, Oregon |------------------------------------- Voice : (503) 935-3709 | Remainder of signature line Data : (503) 935-7883 | under construction.
johnv@tower.actrix.gen.nz (John Veldthuis) (05/10/91)
Quoted from <1991May8.205935.26761@unislc.uucp> by ttobler@unislc.uucp (Trent Tobler): > From article <mykes.2256@amiga0.SF-Bay.ORG>, by mykes@amiga0.SF-Bay.ORG (Mike Schwartz): > > >>2) Is bhs.s the same as bhi.s followed by beq.s? That is what > >> I assumed, bhs is not a true 68000 opcode in any case. > >> > > > > bhs.s means "branch higher or same" and it IS a true 68000 opcode. It > > is an unsigned branch while bge is signed. > > No, it is not a true 68000 opcode. The branching instructions are: > [codes deleted] > > These are not anomalies, and you should find these "basic" features in any > > assembler you consider using. They were in the oldest Metacomco assembler > > available... > > So what do the assemblers do? Generate a BHI and BEQ sequence? > no, with Macro68 you can make up Opcodes that are synonyms for other codes. For example if you fancy calling a MOVE instruction PUT then edit the proper file and assemble it and Macro68 will then use PUT the same as MOVE. Real versatile -- *** John Veldthuis, NZAmigaUG. johnv@tower.actrix.gen.nz ***
sschaem@starnet.uucp (Stephan Schaem) (05/11/91)
No , you wont use HI and EQ, but CC and VS. Usally only CC is nesesary... You could say that CC can replace HS. VS is to check that if you didn't branch it wasn't cause by a carry set... Stephan.
jcs@crash.cts.com (John Schultz) (05/11/91)
In <1991May8.205935.26761@unislc.uucp> ttobler@unislc.uucp (Trent Tobler) writes: [stuff about bhis deleted] >So what do the assemblers do? Generate a BHI and BEQ sequence? bcc (branch carry clear; branch if higher than or same) John
mykes@amiga0.SF-Bay.ORG (Mike Schwartz) (05/12/91)
In article <1991May8.205935.26761@unislc.uucp> ttobler@unislc.uucp (Trent Tobler) writes: >From article <mykes.2256@amiga0.SF-Bay.ORG>, by mykes@amiga0.SF-Bay.ORG (Mike Schwartz): > >>>2) Is bhs.s the same as bhi.s followed by beq.s? That is what >>> I assumed, bhs is not a true 68000 opcode in any case. >>> >> >> bhs.s means "branch higher or same" and it IS a true 68000 opcode. It >> is an unsigned branch while bge is signed. > >No, it is not a true 68000 opcode. The branching instructions are: > >Cond. >0000 BRA always >0001 --- used for the BSR instruction >0010 BHI C and Z clear >0011 BLS C or Z set >0100 BCC C clear >0101 BCS C set >0110 BNE Z clear >0111 BEQ Z set >1000 BVC V clear >1001 BVS V set >1010 BPL N clear >1011 BMI N set >1100 BGE N = V (ie both set or both clear) >1101 BLT N != B (ie one is set and one is clear) >1110 BGT Z clear, and N = V >1111 BLE Z set, and N != V > >> These are not anomalies, and you should find these "basic" features in any >> assembler you consider using. They were in the oldest Metacomco assembler >> available... > >So what do the assemblers do? Generate a BHI and BEQ sequence? > BHS is an alias for BCC. BLO is an alias for BCS. These are TRUE opcodes, meaning you don't need to make them from multiple instructions (like BHI BEQ). >- > Trent Tobler - ttobler@csulx.weber.edu -- **************************************************** * I want games that look like Shadow of the Beast * * but play like Leisure Suit Larry. * ****************************************************
dillon@overload.Berkeley.CA.US (Matthew Dillon) (05/13/91)
In article <1991May10.193126.29483@starnet.uucp> sschaem@starnet.uucp (Stephan Schaem) writes: > > > No , you wont use HI and EQ, but CC and VS. > Usally only CC is nesesary... You could say that CC can replace HS. > VS is to check that if you didn't branch it wasn't cause by a carry > set... > > Stephan. you only need one branch, the confusion is due to motorola never equiviacting BCC and BCS. BCC == BHS >= 0 unsigned comparison BCS == BLO < 0 unsigned BHI > 0 unsigned BLS <= 0 unsigned BGE >= 0 signed comparison BLT < 0 signed BGT > 0 signed BLE <= 0 signed BMI < 0 after test (note that BLT is < 0 after a signed compare, same as BMI except that overflow is checked for. However, after a TST or MOVE instruction, BMI is the same as BLT because the V bit is set to zero). BEQ == 0 BNE != 0 BVC no overflow on signed operation BVS overflow on signed operation -Matt -- Matthew Dillon dillon@Overload.Berkeley.CA.US 891 Regal Rd. uunet.uu.net!overload!dillon Berkeley, Ca. 94708 USA
sschaem@starnet.uucp (Stephan Schaem) (05/13/91)
I have a question about Macro68... More of a problem than a question. My problem is with EQU and labels (Loacal labels). to give an example: Start: nop 1$ nop 2$ nop etc... Start1 equ 1$ Start2 equ 2$ Sometime I use the address has an offset of the subroutine. Or for in data structure... But anyway, The problem is that during pass 1 it seem that the equ dont 'equate' and macro68 optimize ( Start-Start1(Ax) -> ,(Ax)) Than during pass 2 the value 'equate' and cause an error of course since the program size changed. I know way around that, like replacing all my local labels by their 'real' names and all branching names... Also is there a way to make Macro68 use local labels name has strings and not values? (To be genim2 compatible..) I'm asking all that because I switching over to Macro68! Leaving Genim2 aside... I found my problem with macros, Macro68 dont like ELSEIF but ELSE?!?!!? Even with the same def in the custom file... Maybe someone know why. Macro68 is around 99% compatible with Genim2, and is around 10 time faster!!!! To give an example.I change only incdir (Macro68 dont like path list), not a big deal but would me nice, to make a small game written for devpac compile with macro68 (multitasking). So to give justice, I will know support Macro68 over Genim2... Also what is the best way to make the profiler work on a A3000? Stephan.