peterl@ibmpcug.co.uk (Peter Leaback) (12/07/90)
Because of the way memory works, each time the processor fetches an
instruction which crosses a Quad Word boundary an extra cycle is used.
So if 4 words are fetched then an extra cycle can be saved if it is Q.W.
aligned, but if 5 words are fetched then it may not make the difference.
Anyway the effect is slight and not as much as 5% on a good chunk of
code.
Talking about an ARM3, it makes more of a difference because the cache
fetches Q.W. aligned data, so it may fetch data that isn't needed.
>idea - although I haven't studied the PRMs or Intel's ARM chip set data
Intel !! wash your mouth out.
Peter Leaback.
--
Automatic Disclaimer:
The views expressed above are those of the author alone and may not
represent the views of the IBM PC User Group.
-- andras@alzabo.uucp (Andras Kovacs) (12/08/90)
In article <1990Dec7.012835.3319@ibmpcug.co.uk> peterl@ibmpcug.co.uk (Peter Leaback) writes: > >Because of the way memory works, each time the processor fetches an >instruction which crosses a Quad Word boundary an extra cycle is used. >So if 4 words are fetched then an extra cycle can be saved if it is Q.W. >aligned, but if 5 words are fetched then it may not make the difference. >Anyway the effect is slight and not as much as 5% on a good chunk of >code. > I wouldn't say 'because of the way memory works'. This characteristics of the Archimedeses exists because the memory controller able to exploit the fast page mode access capabilities of modern DRAM's: "MEMC uses the page mode access capability of DRAMs, where, once a row address has been strobed into the DRAM, any column in that row may be accessed merely by strobing in the new column address." (VL86C010 32-bit RISC MPU and Peripherals Users Manual, VLSI Technology, Inc., 1989). 5% can make a big difference deep inside a nested loop! -- Andras Kovacs andras@alzabo.UUCP
denis@gec-rl-hrc.co.uk (Denis Howe (G13) x2220) (12/10/90)
In article <1990Dec7.012835.3319@ibmpcug.co.uk> peterl@ibmpcug.co.uk (Peter Leaback) writes: >>idea - although I haven't studied the PRMs or Intel's ARM chip set data > >Intel !! wash your mouth out. > >Peter Leaback. And this from the IBM PC User's Group!