scott@labtam.labtam.oz (Scott Colwell) (12/19/90)
On looking at the VL86C020 (ARM2) data sheet, I noted that the memory interface is clocked by a different clock (MCLK) to the core(FCLK). The memory interface can be clocked at up to 12.5MHz with clock stretching allowed in addition to the wait pin for extending cycles. The core can be clocked at up to 20MHz totally asynchronously to the memory interface. (source: "Acorn Risc Machine Family Data Manual", VLSI Tech. 1990) The data sheet talks about the core 'synchronising to MCLK' when going to memory and staying synchronised while doing sequential accesses. If this actually means that the core clock changes frequency, the mind boggles. Logic to do this would have very nasty effects on the clock skew etc on chip. Doesn't this stop you using on chip delay line and pll techniques ? Does anybody have any MTBF data for the synchroniser(s) that must exist in either the clock circuitry or between the core and the memory I/F ? The data sheet shows the sync'ing to MCLK taking one FCLK and two MCLK cyles and one FCLK cycle for the sync to FCLK. There seems to be some possiblity of the core staying synchronised between accesses if some conditions are met. Does anybody have any data on how often this does happen ? Is it possible/practical to write e.g. blt code that avoids these synchronisations ? (This is required if the code is to come anywhere near memory bandwidth as is possible with the Intel 960.) In general I consider this style of interface to be a bad idea. If there are no synchronisers built in, the designer can either make the memory purely synchronous to the core (with no extra MTBF problems over soft errors etc.) or include external synchronisers with known MTBFs and latencies if it makes sense to have the memory asynchronous to the core. Before anybody jumps on me saying that the VL86C020 method allows cheap memory interfaces, I accept that this may save you some hardware cost but the value of this saving is questionable in comparison to what has been sacrificed. This is 'modern' equivalent to the old style of asynchronous 'ready' lines that were popular on CISC micros a few years ago. It is rather telling that this is the only micro claiming high performance that I have seen in the last couple of years that didn't allow the memory interface to be synchronous. -- Scott Colwell Senior Design Engineer Labtam Australia net: scott@labtam.oz.au Melbourne, Australia phone: +61-3-587-1444