mark@acorn.co.uk (Mark Taunton) (04/17/91)
In article <4826@syma.sussex.ac.uk> gavinw@syma.sussex.ac.uk writes: >Two enhancements to future ARMs that I would like to see are > >i) 'modify offset-register' writeback addressing-modes >ii) trap register-values-outside-given-range to speed up range >checking. Just to remind people, the R in ARM stands for RISC (I won't raise the issue of what the A stands for these days :-|), and RISC, at least by most commonly-encountered definitions stands for "Reduced Instruction Set Computer/Computers/Computing/Complexity/C<whatever>". I fear that the second proposed "enhancement" doesn't really fall into this category, (in terms of the original basis of RISC processor design) although I accept that it can still be useful. However if you need to do range-checking on a constant range, perhaps the following may help. The "obvious" direct coding for range checks on signed quantities is (in RISC iX assembler syntax): cmp rx, #lower_bound @ x < lower_bound ? swilt SWI_range_error cmp rx, #upper_bound @ x > upper bound ? swigt SWI_range_error [I have assumed you really do want a "trap", so have used a conditional SWI above - you can implement the SWI handling yourself under either RISC OS or RISC iX. Alternatively, a simple Bcc (or, to allow diagnosis assuming the calling routine will not continue or has saved r14, a BLcc) to suitable handler code might be used instead.] OK, that's 4 instructions (perhaps more, if lower_bound or upper bound can't be represented as an ARM immediate field, or they're not already in a pair of registers). If lower_bound is actually 0, switching to unsigned working helps a lot: cmp rx, #upper_bound @ (unsigned)x > upper_bound ? swihi SWI_range_error This can also be adjusted for the unlikely possibility of lower_bound -ve, upper bound 0. Even for the general case (neither bound 0), assuming there is a spare register around, you can still get it down by one instruction by treating things as unsigned: sub rtemp, rx, #lower_bound cmp rtemp, #upper_bound-lower_bound swihi SWI_range_error or if the particular constant values work out better: cmp rx, #upper_bound {r_upper_bound} rsble rtemp, rx, #lower_bound {r_lower_bound} swigt SWI_range_error (We need to use rsb and a temporary since ARM has no reverse compare instruction.) On the second idea ('modify offset-register' writeback addressing-modes) I am not at all clear what is meant. Can you elaborate? Mark Taunton, Acorn Computers Ltd. mark@acorn.co.uk
hughesmp@vax1.tcd.ie (04/22/91)
It's all very nice talking about loads of new instructions for future ARMs, but they would only be of use to home users, who wrote their own code, because anything commercially released using the instructions wouldn't work on lesser chips. The alternative would be to write a 'ARM3' patch module, and so on, for each chip down the range, as each new chip was released, which would trap undefined instrucions and do them in software... Not that nice really. I'd prefer to see basic speed, video, cache, and memc improvements first... Backwards compatibility is of prime importance in developing further chips in the series. (I'm not saying the ARM3 is slow, or has a bad cache, I just don't have one, but we can always do with more speed...) Merlin.