astevens@acorn.co.uk (Ashley Stevens) (05/08/91)
In article <DBH.91May6201750@asun4.doc.ic.ac.uk> dbh@doc.ic.ac.uk (Denis Howe) writes: >And while we're on the subject of MEMC, can anyone say exactly what >the effect of the memc_roms program on the Newcastle server is? It >sets the MEMC speed (cycle time) for the ROMs to, what my VLSI data >book says is "Not Meaningful" but which extrapolation from the other >possibilities (450, 325, 200ns) would suggest is actually 75ns. It is meaningful. It is actually 200nS with 60nS access 'nibble-mode'. This means that ROM accesses are in groups of 4 (like DRAM accesses) where the first is 200nS, and the subsequent three are 60nS accesses. (I know of no (large) ROMs that have this feature - if you do, let us know!) > It does produce a speed-up (~25% for > FOR I%=0 TO 10000:NEXT >) and doesn't seem to crash my A410. Am I just lucky? Yes, you are just lucky! In article <9887@suns6.crosfield.co.uk> djhr@crosfield.co.uk (dave redman) writes: >I am curious abut something else though.. In my VLSI data book it says the ARM3 >runs at 20Mhz.. does this mean a 30Mhz device is just a 20Mhz device that >happens to run at 30Mhz or is my Nov. 1990 VLSI data book already out of date ? Yes it is out of date. All ARM3's are now rated at 25Mhz. Your 30MHz one is just one that may (or may not!) work at 30MHz. ___________________________________________________________________ Ashley Stevens astevens@acorn.co.uk Acorn Computers, 645 Newmarket Rd, Cambridge, UK. Tel.(0223) 214411