berg@cip-s05.informatik.rwth-aachen.de (AKA Solitair) (12/10/90)
According to some computer magazine, there is supposed to be a bug
in "version 3" of the 486 regarding interrupt processing.
The bug (discovered by a UK firm) alledgedly is especially important
for 'networked' 486's. They say it is not easy to reproduce the bug.
And neither Intel nor Novell have been able to reproduce the bug
(so they say :-).
Does anyone have more specific info about this bug? (or for that matter,
any known bugs of the 486?)
If you send me mail, please take care to use the address in the signature.
Thanks.
--
Sincerely, berg%cip-s01.informatik.rwth-aachen.de@unido.bitnet
Stephen R. van den Berg.
"I code it in 5 min, optimize it in 90 min, because it's so well optimized:
it runs in only 5 min. Actually, most of the time I optimize programs."james@bigtex.cactus.org (James Van Artsdalen) (12/17/90)
In <3733@rwthinf.UUCP>, berg%cip-s01.informatik.rwth-aachen.de@unido.bitnet wrote: > According to some computer magazine, there is supposed to be a bug > in "version 3" of the 486 regarding interrupt processing. B step I think. C step does not have the bug (I think, he says, trying to remember). But in any case there is a work-around, so even machines with B step parts should be OK if properly designed. > The bug (discovered by a UK firm) alledgedly is especially important > for 'networked' 486's. They say it is not easy to reproduce the bug. It was discovered by Compaq in Houston. The 486 has a four word deep "write buffer". When the CPU issues a write, it is put in the queue and written as soon as the bus is idle. When the 486 receives an interrupt request, it does two special "interrupt acknowledge" cycles. The first one is a "dummy" cycle that causes the interrupt controller to latch its interrupt input pins, and the second acknowledge cycle reads the actual vector from the interrupt controller. Those two interrupt acknowledge cycles are supposed to be guaranteed adjacent. The bug is that sometimes the write buffer can do a cycle between the two INT/ACK cycles. Some interrupt controllers can't handle this. -- James R. Van Artsdalen james@bigtex.cactus.org "Live Free or Die" Dell Computer Co 9505 Arboretum Blvd Austin TX 78759 512-338-8789