[comp.research.japan] An Overview of TRON

jdm@cs.wvu.wvnet.edu (James D Mooney) (03/14/91)

			AN OVERVIEW OF TRON

			    Jim Mooney
		Dept. of Statistics and Computer Science
			West Virginia University
			Morgantown, WV 26506 USA
			VOICE:  +1 304 293 3607
			FAX:    +1 304 293 2272

Updated March 13, 1991

The following is some general information on the TRON project.  I
believe this information is current and correct as of the given date,
though it certainly is not complete.  I apologize for any errors or
omissions.  A short annotated bibliography of English language
publications is also included.

The TRON project was begun in 1984 by Dr. Ken Sakamura at the University
of Tokyo.  Its ultimate objective is to support what is envisioned as
"Highly Functionally Distributed Systems" or HFDS, that is, networks
that span the globe, connecting large computers, personal workstations,
and a multitude of "intelligent objects" such as appliances,
environmental control systems, cameras, automobiles, etc., etc., in
which computers are embedded.  Today TRON is a major industrial project
being carried out by a consortium of over 145 companies.  In contrast to
other well-known Japanese initiatives such as the Fifth Generation
project and the Sigma project, TRON is in no way government sponsored.

TRON stands for The Realtime Operating system Nucleus.  The total
project includes a specification for a TRON CPU chip, several
types of operating system interfaces, and a number of auxiliary
subprojects.

Each project is defined by a set of specifications which focus on the
interface and functionality and deliberately leave room for design
variations.  It is intended that the specifications be publicly
available and it is hoped that many developers will produce
implementations which meet the specifications.

The OS subprojects include:

	ITRON (Industrial TRON), specialized for (embedded) control
	of intelligent objects;

	BTRON (Business TRON), specialized for control of
	workstations;

	CTRON (Communication, Central and Common-Use TRON),
	specialized for managing processing on larger computers
	and communication between computers;

	MTRON (Macro TRON), intended to provide overall intelligent
	control to the HFDS.

Other related projects that have been initiated under the TRON
umbrella include

	TULS (TRON Universal Language System), a specification
	language for describing system interfaces;

	TAD (TRON Application Databus), a data format specification
	for information exchange;

	TACL (TRON Application Control-Flow Language), an interactive
	user-interface language for BTRON systems.

	TOBUS, a system bus architecture, and an extended version
	TOXBUS for multiprocessor environments.

My own detailed knowledge is limited to CTRON.  I will give what
information I have on the other projects.

The TRON CPU is a powerful (CISC style) 32-bit microprocessor extensible
to 64-bit data paths and addresses.  It is especially designed for ITRON
and BTRON systems, but can run other types of systems as well.  Versions
of this chip have now been implemented independently by at least half a
dozen Japanese manufacturers.

ITRON is an OS interface specification for small realtime executives
used in embedded applications such as robotics or factory automation.
A micro subset and a full version have been designed.  ITRON is intended
especially for implementation on the TRON CPU, but has been implemented
for several other architectures as well, including IBM-PC.

BTRON is a design for an OS program interface and human interface for
high-performance, multilingual workstations.  Emphasis is on
sophisticated user interfaces and high-level information storage.  A
unique keyboard has been designed for Japanese and multilingual use.
Special attention is given to the requirements of handicapped users in
the BTRON design.

Several companies have produced BTRON workstations.  A variety of
microprocessors has been used.

CTRON is a very large specification for system interfaces appropriate on
larger systems acting as network servers.  The full specifications have
been published in 8 volumes totalling over 3000 pages.
These are still draft versions.  Implementation studies are in progress.
Language bindings for C, Ada, and CHILL are also being defined.

Recent CTRON work has focused on issues of reliability and validation.
A design guide for fault tolerance has also been published.  A
micro-CTRON subset has been defined, and subsetting issues are being
clarified.

Recently the CTRON Committee began a series of portability experiments
to investigate in an orderly way the problems of porting the two levels
of the CTRON OS, and CTRON applications, to a number of target
environments.

MTRON and the newer subprojects are still in relatively early stages of
development.  However, the project is maturing.  Recent emphasis has
been placed on implementation studies, validation, and systemwide issues
such as fault tolerance.  A "TRON house" has been built outside Tokyo,
to demonstrate the intelligent control systems envisioned by the HFDS.
A TRON automobile, a TRON office building, and a TRON city are in the
planning stages.

The initial TRON papers and documents were all in Japanese.  However,
IEEE MICRO in 1987 devoted an entire issue to TRON (Vol. 7, No. 2, April
1987). This issue is still one of the best widely-available detailed
introductions to the TRON project. A second excellent reference is the
October 1989 issue of Microprocessors and Microsystems (Vol. 13, No. 8).
Other occasional articles have appeared in English publications and
conference proceedings.  Most of these are cited in the attached
bibliography.  A brief description of the TRON house, with photos,
appears in the April 1990 issue of IEEE MICRO.

Dr. Sakamura remains the "guiding spirit" of most TRON projects.
However, work continues today under the direction of a large industrial
consortium called the TRON Association.  This association was formed in
Japan in 1986 and officially incorporated in 1988.  Membership as of
1990 included about 150 companies.  Although all activities to date have
taken place in Japan, participation in the TRON association has never
been restricted by nationality.  Membership is open to "corporate bodies
and organizations that share the goals of the association."  Annual dues
range from 500,000 yen (currently about $3333 U.S.) to 3,000,000 yen
(about $20,000) depending on degree of participation.  The current
membership list includes such familiar non-Japanese names as ASCII
Corp., AT&T, Digital Equipment, IBM, Intel, Motorola, Northern Telecom,
Olivetti, Siemens, Texas Instruments, and Victor (most of these are
represented by their Japanese divisions).

Recently several additional membership categories have been established.
Individuals can now become members for a one-time entry fee of 5000 yen
(about $33) and an annual fee of 10,000 yen ($67).  The TRON Association
conducts a variety of meetings and conferences.  So far there have been
four international conferences (in Tokyo) with English proceedings and
translations.  The proceedings have been published by Springer-Verlag's
Tokyo division (see the bibliography).

The TRON association also publishes the TRON Project Bimonthly (formerly
Quarterly Report), a dual-language publication available to members
only, and TRON News and Information, a monthly English-language
newsletter.  Steven Searle is the principal English-language contact at
the TRON Association.  He will be glad to place you on a mailing list,
provide copies of the newsletter, and answer any questions more
accurately than I can.  Mr.  Searle can be contacted at the following
address:

	Steven J. Searle
	TRON Association
	5th floor, Tomoecho Annex-II
	3-8-27, Toranomon, Minato-ku
	Tokyo 105 JAPAN
	Tel: +81 3 3433 6741
	FAX: +81 3 3433 5003

Mr. Keijiro Hirota is the Executive Director of the TRON Association.  He
may be reached at the same address.

Dr. Sakamura himself can be contacted at the University of Tokyo:

	Dr. Ken Sakamura
	Dept. of Information Science
	Faculty of Science, University of Tokyo
	3-1, Hongo 7-chome, Bunkyo-ku
	Tokyo 113 JAPAN
	FAX: +81 3 3779 5753

Detailed specifications for at least some of the TRON projects are
available for purchase.  TRON Association membership is not required.
Selected specifications for ITRON, BTRON, and the TRON CPU are
available in English from the TRON Association.  Current prices
are:

			MEMBERS	NONMEMBERS
	micro-ITRON	Y8,000	Y12,000
	ITRON2					in preparation
	BTRON1		Y67,000	Y100,000	in 7 volumes
	BTRON/286
	  summary	Y2,000	Y3,000
	TRON CHIP	Y4,000	Y10,000

CTRON specifications have been published in preliminary versions in both
Japanese and English.  The "version 2" series is now appearing; version
3 is scheduled by the end of 1991.  Because of their bulk they have been
fairly expensive.

A new publishing arrangement has been established to make these
volumes available more economically.  The Version
2 Specifications (in English) can be ordered from

	Ohmsha, Ltd.
	3-1 Kanda Nishiki-cho,
	Chiyoda-ku, Tokyo 101 JAPAN
	PHONE: +81 3 233-0681
	FAX: +81 3 293-2824

or	IOS
	Van Diemenstraat 94
	1013 CN Amsterdam
	Netherlands
	FAX: +31 20 22 60 55

or	IOS
	PO Box 2848
	Springfield, VA 22152-2848
	USA

There are 8 volumes in the Version 2 CTRON Specifications.  I recommend
especially Volume 1, Outline of CTRON, $65 (U.S.), postpaid (from the
U.S. address, I assume) if payment is made with the order.  The price
for the complete series is $1100 U.S.  A descriptive brochure and order
form is also available.


		ANNOTATED ENGLISH LANGUAGE BIBLIOGRAPHY

	Datamation.  Japan's TRON tactics.  Datamation, Vol. 33, No. 19,
	Oct. 1, 1987, pp. 76/21 ff. (International edition).

		An early overview of the TRON project.

	Electronic Design.  Instruction Set Architecture Prepares
	Systems for the 1990s.  Electronic Design, Vol. 36, No. 3,
	Feb. 4, 1988, pp. 33 ff.

		A description and review of the TRON CPU architecture
		and its potential impact on the industry.

	Imai, Y., et al.
	An implementation based on the BTRON specification.  in
	IEEE COMPCON Spring 1988 Digest of Papers, pp. 22-24.

	Kobayashi, M., et al.
	The software structure of extended nucleus based on the
	BTRON specification.  Proc. 1987 Fall Joint Computer Conf.,
	pp. 153-158.

	Sakamura, Ken (ed).  IEEE MICRO Special issue on TRON.  Vol 7,
	No. 2, April 1987.

		Articles include: The TRON Project; Architecture of
		the TRON VLSI CPU; Configuration of the CTRON Kernel;
		Introduction to ITRON; BTRON: the Business-oriented
		Operating System.

	Sakamura, Ken (ed.)
	TRON Project 1987: Open-Architecture Computer Systems
	(Proceedings of the Third TRON Project Symposium)
	Springer-Verlag, Tokyo, 1987

		Proceedings of the first *international* (English
		language) TRON symposium, Tokyo, November 1987.
		Includes a TRON overview; overviews of ITRON and
		BTRON plus implementation papers;  overview of
		CTRON plus several design papers;  overview of
		TRON CPU plus design and implementation papers.

	Sakamura, Ken (ed.)  IEEE MICRO special issue on the 32-Bit
	Microprocessor in Japan.  Vol. 8, No. 2, April 1988.

		Description of three new microprocessor implementations,
		two of which are TRON CPUs, and related projects.	

	Sakamura, Ken (ed.)
	TRON Project 1988: Open-Architecture Computer Systems
	(Proceedings of the Fifth TRON Project Symposium)
	Springer-Verlag, Tokyo, 1988

		Proceedings of the second international TRON
		symposium, Tokyo, December 1988.  Includes design
		concepts for TULS and MTRON;  ITRON implementation
		papers;  BTRON concepts and implementations; TACL
		language;  CTRON design, implementation, and
		commentary;  lots of TRON CPU implementations.

	Sakamura, Ken, and Sprague, Richard.  The TRON Project.
	BYTE, Vol 14, No. 4, April 1989, pp. 292-301.

		An overview of the status of TRON, with
		emphasis on BTRON and the TRON CPU.  A sidebar by
		editor Janet Barron discusses TRON's prospects for
		acceptance in the U.S.

	Sakamura, Ken (ed.).  Special Issue of Microprocessors and
	Microsystems: Understanding the TRON Architecture.  Vol. 13,
	No. 8, Oct. 1989.

		Contains a TRON Project overview by Dr. Sakamura;
		one article each on the TRON CPU, ITRON, BTRON,
		and CTRON; four viewpoints on the impact of TRON
		in the U.S. and Europe; an interview with Dr.
		Sakamura;  short notes on current TRON activities.

	Sakamura, Ken (ed.)
	TRON Project 1989: Open-Architecture Computer Systems
	(Proceedings of the Sixth TRON Project Symposium)
	Springer-Verlag, Tokyo, 1989

		Proceedings of the third international TRON
		symposium, Tokyo, December 1989.  Includes 
		implementation articles for ITRON, BTRON,
		CTRON, and the TRON CPU, and a keynote by
		Dr. Sakamura on "The Computerized Society",
		with overviews of the TRON house, automobile,
		and city.

	Sakamura, Ken. The TRON Intelligent House.  IEEE MICRO,
	Vol. 10, No. 2, Apr. 1990, pp. 6-7.

		A brief overview of the experimental TRON
		house in Tokyo, with photos.

	Sakamura, Ken (ed.)
	Proceedings of the first Software Portability Symposium.
	TRON Association, Sept. 1990

		Proceedings of a symposium held to begin the
		portability experiments of the CTRON Committee.
		Contains papers on the CTRON experiment specifically,
		as well as on general portability issues.

	Sakamura, Ken (ed.)
	TRON Project 1990: Open-Architecture Computer Systems
	(Proceedings of the Seventh TRON Project Symposium)
	Springer-Verlag, Tokyo, 1990

		Proceedings of the fourth international TRON
		symposium, Tokyo, December 1990.  25 papers
		further describe implementations of ITRON, BTRON,
		CTRON, and the TRON Chip.  Performance and
		portability are stressed.  Five papers describe
		work outside Japan.

	Wasano, T., et al.
	Design Principles and Configuration of CTRON.
	Proc. 1987 Fall Joint Comp. Conf., pp. 159-166.