pefv700@perv.pe.utexas.edu (02/26/91)
I have 2 executables that are "made" using the same sources files. The only difference is that for one a cpp(1) macro is defined, for the other it is not. It is obvious that if I keep everything in one directory, the best I can do is to work on one, then make would recompile all of the source files and then the other could be worked on. This is acceptable. However, I cannot think of a good way to let make know that executable 1 needs the .o files to have been made with the macro defined while for executable 2 it is just the opposite. Lastly, my home directory has a $ in it (thanks to an NFS mount to a VAX :-(). I would like to do something like: PROG=$(HOME)/name $(PROG): object files... cc -o $(PROG) options... object files... libs... However, the shell (in the cc line) keeps interpreting the $. Am I out of luck on this one or can this be fixed? Thanks, Chris
cpcahil@virtech.uucp (Conor P. Cahill) (02/26/91)
pefv700@perv.pe.utexas.edu writes: >I have 2 executables that are "made" using the same sources files. The only >difference is that for one a cpp(1) macro is defined, for the other it is not. The easiest way to do this is to create a new rule: .c.p: if [ -s $*.o ]; then \ mv $*.o sv.$*.o; \ fi $(CC) -c $(CFLAGS) $(SPECIAL_CPP_FLAG) $< mv $*.o $*.p if [ -s sv.$*.o ]; then \ mv sv.$*.o $*.o; \ fi and have the program that needs the define depend upon objects with a .p extension. if they are all the same sources you could do the following: SRCS=name1.c name2.c ... PGM1OBJS=$(SRCS:.c=.o) PGM2OBJS=$(SRCS:.c=.p) pgm1: $(PGM1OBJS) cc -o $@ $(PGM1OBJS) pgm2: $(PGM2OBJS) cc -o $@ $(PGM2OBJS) >Lastly, my home directory has a $ in it (thanks to an NFS mount to a VAX :-(). >I would like to do something like: >$(PROG): object files... > cc -o $(PROG) options... object files... libs... put single quotes around the $(PROG). For example: cc -o '$(PROG)' options... object files... libs... Note that you should only do this for shell command lines. Makefile directives may get confused. -- Conor P. Cahill (703)430-9247 Virtual Technologies, Inc. uunet!virtech!cpcahil 46030 Manekin Plaza, Suite 160 Sterling, VA 22170
tif@doorstop.austin.ibm.com (Paul Chamberlain) (02/26/91)
cpcahil@virtech.uucp (Conor P. Cahill) writes: >pefv700@perv.pe.utexas.edu writes: >>I have 2 executables that are "made" using the same sources files. The only >>difference is that for one a cpp(1) macro is defined, for the other it is not. >The easiest way to do this is to create a new rule: That's alot better than my way. But just to give an alternative method: Well, I got it figured out. Below I have included a makefile for two hypothetical executables that use the same .c's. A fringe benefit is that even if you only have one executable, using this style of make file will allow you to remove all the .o's and it still won't recompile anything unless a .c or .h changed. Paul Chamberlain | I do NOT speak for IBM. IBM VNET: PAULCC AT AUSTIN 512/838-9662 | ...!cs.utexas.edu!ibmchs!auschs!doorstop.austin.ibm.com!tif # This is a really bizarre makefile that allows two executables to be made # from one set of source. In this example, the exe's are to be compiled # with slightly different compile lines and libraries. This should handle # all manner of interrupted and restarted compiles. OBJ = obj1.o obj2.o obj3.o HFILES = local1.h local2.h CFLAGS = -O $(NAME) LDFLAGS = $(OTHER_LIB) # by default, make both executables all: exe1 exe2 clean: rm -f *.o making.exe1 making.exe2 # This will prevent recompilation if everything is # up to date even if no .o's are around. exe1: $(OBJ:.o=.c) exe1.c $(HFILES) if test ! -f making.exe1;then make clean;fi touch making.exe1 $(MAKE) NAME=-DEXE1 OTHER_LIB=-lx exe1.make exe1.make: $(OBJ) exe1.o $(CC) $(CFLAGS) $(OBJ) exe1.o $(LDFLAGS) -o exe1 # This will prevent recompilation if everything is # up to date even if no .o's are around. exe2: $(OBJ:.o=.c) exe2.c $(HFILES) if test ! -f making.exe2;then make clean;fi touch making.exe2 $(MAKE) NAME=-DEXE2 exe2.make exe2.make: $(OBJ) exe2.o $(CC) $(CFLAGS) $(OBJ) exe2.o $(LDFLAGS) -o exe2
gsf@ulysses.att.com (Glenn S. Fowler) (02/27/91)
In article <44683@ut-emx.uucp> pefv700@perv.pe.utexas.edu writes: >I have 2 executables that are "made" using the same sources files. The only >difference is that for one a cpp(1) macro is defined, for the other it is not. > >It is obvious that if I keep everything in one directory, the best I can do is >to work on one, then make would recompile all of the source files and then the >other could be worked on. This is acceptable. However, I cannot think of a >good way to let make know that executable 1 needs the .o files to have been >made with the macro defined while for executable 2 it is just the opposite. depending on your situation this might be suitable given x.c, make a new file x-debug.c (you pick the name) that contains #define DEBUG 1 /* you pick the macros */ #include "x.c" then use makefile assertions like x : x.o ... ... x-debug : x-debug.o ... ... Glenn Fowler (908)-582-2195 AT&T Bell Laboratories, Murray Hill, NJ uucp: {att,ucbvax}!ulysses!gsf internet: gsf@ulysses.att.com