rcd@ico.isc.com (Dick Dunn) (01/17/91)
aland@informix.com (Colonel Panic) writes: > [I wrote] > >...Conventional wisdom (such as it is:-) says > >that the PC/AT bus is seldom a limiting factor, unless you put memory out > >there, which is rare for 386es... ... > I wouldn't call this "rare" anymore. AT&T (and others) have been > shipping 386s that can support 40MB or more for several years. You've got what I said turned around. I'm saying that 386 boxes rarely have memory on the ISA bus--it's only used as the I/O bus in 386 machines. Certainly you won't have 40 Mb of memory on an ISA bus--it can't support that much physical address space! My point was that the bus load from putting memory on the ISA bus would be disastrous, but "nobody" does that for 386es, so it's not a problem. > You wouldn't think the ISA bus was so nifty if you were trying to do > DMA over it (or use memory-mapped devices) on an ISA-bus machine with > over 16MB of memory on it... That's definitely a problem...although it really focuses on the DMA controllers (wretched devices for various reasons) more than the I/O bus. Somewhere along the way to moving memory off the ISA bus, someone should have come up with a better DMA controller that also had a way to get to more memory. -- Dick Dunn rcd@ico.isc.com -or- ico!rcd Boulder, CO (303)449-2870 ...Mr. Natural says, "Use the right tool for the job."
tmh@keks.FOKUS.GMD.DBP.DE (Thomas Hoberg) (01/30/91)
In article <1991Jan16.185851.2419@ico.isc.com>, rcd@ico.isc.com (Dick Dunn) writes: |> > You wouldn't think the ISA bus was so nifty if you were trying to do |> > DMA over it (or use memory-mapped devices) on an ISA-bus machine with |> > over 16MB of memory on it... |> |> That's definitely a problem...although it really focuses on the DMA |> controllers (wretched devices for various reasons) more than the I/O bus. |> Somewhere along the way to moving memory off the ISA bus, someone should |> have come up with a better DMA controller that also had a way to get to |> more memory. |> -- Nobody (but the floppy) really uses those wretched devices. These so called bus mastering controllers just pull the DREQ lines to get the CPU off the bus. The DMA they do themselves. But no DMA controller, however smart, can circumvent the fact that there are only 24 address lines on the ISA bus. |> Dick Dunn rcd@ico.isc.com -or- ico!rcd Boulder, CO (303)449-2870 |> ...Mr. Natural says, "Use the right tool for the job." ---- Thomas M. Hoberg | UUCP: tmh@bigfoot.first.gmd.de or tmh%gmdtub@tub.UUCP c/o GMD Berlin | ...!unido!tub!gmdtub!tmh (Europe) or D-1000 Berlin 12 | ...!unido!tub!tmh Hardenbergplatz 2 | ...!pyramid!tub!tmh (World) Germany | BITNET: tmh%DB0TUI6.BITNET@DB0TUI11 or +49-30-254 99 160 | tmh@tub.BITNET
rcd@ico.isc.com (Dick Dunn) (01/31/91)
tmh@keks.FOKUS.GMD.DBP.DE (Thomas Hoberg) writes: > ...rcd@ico.isc.com (Dick Dunn) writes: ... > |> Somewhere along the way to moving memory off the ISA bus, someone should > |> have come up with a better DMA controller that also had a way to get to > |> more memory. ... > ...But no DMA controller, however smart, can > circumvent the fact that there are only 24 address lines on the ISA bus. That's true, but that's not what I meant. Once again, memory doesn't go on the ISA bus. Since the DMA controllers go on the main board, in theory they could have access to the (private, non-ISA, >24-bit) memory bus, and one could imagine a design which would give them access to the ISA bus on one side and memory on the other, so that they could handle transfers in/out of full memory. (That's a theoretical argument. It would have had to happen much earlier for it to work...in a practical sense, it's too late for that to happen on ISA-based machines, so EISA seems to be the answer.) -- Dick Dunn rcd@ico.isc.com -or- ico!rcd Boulder, CO (303)449-2870 ...Mr. Natural says, "Use the right tool for the job."
cpcahil@virtech.uucp (Conor P. Cahill) (01/31/91)
In article <296@bigfoot.first.gmd.de> tmh@keks.FOKUS.GMD.DBP.DE (Thomas Hoberg) writes: > >In article <1991Jan16.185851.2419@ico.isc.com>, rcd@ico.isc.com (Dick >Dunn) writes: >|> Somewhere along the way to moving memory off the ISA bus, someone should >|> have come up with a better DMA controller that also had a way to get to >|> more memory. >|> -- >But no DMA controller, however smart, can >circumvent the fact that there are only 24 address lines on the ISA bus. The address lines on the ISA bus don't matter in this case because most, if not all, 386 systems provide a second 32-bit memory bus for system memory. It *should* be possible to find a DMA controller that will allow you to move data from an ISA card to a 32 bit memory address. -- Conor P. Cahill (703)430-9247 Virtual Technologies, Inc. uunet!virtech!cpcahil 46030 Manekin Plaza, Suite 160 Sterling, VA 22170
tmh@bigfoot.FOKUS.GMD.DBP.DE (Thomas Hoberg) (02/12/91)
In article <1991Jan31.010126.23088@virtech.uucp>, cpcahil@virtech.uucp (Conor P. Cahill) writes: |> In article <296@bigfoot.first.gmd.de> tmh@keks.FOKUS.GMD.DBP.DE (Thomas Hoberg) writes: |> > |> >In article <1991Jan16.185851.2419@ico.isc.com>, rcd@ico.isc.com (Dick |> >Dunn) writes: |> >|> Somewhere along the way to moving memory off the ISA bus, someone should |> >|> have come up with a better DMA controller that also had a way to get to |> >|> more memory. |> >|> -- |> >But no DMA controller, however smart, can |> >circumvent the fact that there are only 24 address lines on the ISA bus. |> |> The address lines on the ISA bus don't matter in this case because most, |> if not all, 386 systems provide a second 32-bit memory bus for system |> memory. It *should* be possible to find a DMA controller that will allow |> you to move data from an ISA card to a 32 bit memory address. |> Ok, I was thinking in terms of a bus mastering DMA controller, where the bus master is generating the appropriate addresses... Actually Intel itsself developed such a beast (maybe 82350?). Anyway SUN used it in it's orphaned Roadrunner series of 386 Unix boxes. It has two modes: 1) PC compatible, 2) 32-bit. Because the DMA unit sits between the CPU and the ISA bus, it can generate 32-bit addresses for the CPU thus obviating one of the usual ISA limits. Bus mastering on that ISA bus was out, however, as was the virtual DMA that SUN loves so much. ---- Thomas M. Hoberg | UUCP: tmh@bigfoot.first.gmd.de or tmh%gmdtub@tub.UUCP c/o GMD Berlin | ...!unido!tub!gmdtub!tmh (Europe) or D-1000 Berlin 12 | ...!unido!tub!tmh Hardenbergplatz 2 | ...!pyramid!tub!tmh (World) Germany | BITNET: tmh%DB0TUI6.BITNET@DB0TUI11 or +49-30-254 99 160 | tmh@tub.BITNET