hart@cp1.UUCP (08/06/84)
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AMATEUR RADIO RESEARCH AND DEVELOPMENT
CORPORATION (AMRAD)
VADCG TERMINAL NODE CONTROLLER (TNC)
DAUGHTER BOARD VDS-1
INSTRUCTION MANUAL
JULY 1, 1984
NOTICE NOTICE NOTICE
Amateu Radi Researc an Developmen (AMRAD i not-for-
profi organization incorporate i th Stat o Virginia
AMRA i dedicate t th advancemen o th state-of-the-ar o
Amateu Radi communications Thi boar wa designe b AMRA
an Terr Fox WB4JF t allo th continuatio o th us o th
Vancouve Amateu Digita Communication Grou (V.A.D.C.G.
Termina Nod Controlle (TNC) Thi boar i sol a retrofi
subsyste t th VADC TNC an a such n warrantie ar
expresse o implied eithe fo it prope operation o th
proper operation of the host TNC board.
I i requeste tha al user o thi boar suppor AMRA
b joinin thi organization Tha wa al user wil receiv
th AMRA_Newsletter whic wil contai updates corrections
an enhancement t th VDS-1 alon wit wealt o othe
informatio regardin packe radio an Amateu Radi i general.
To join AMRAD, send $15.00 to:
Amateur Radio Research and Development Corporation
William P. Pala, WB4NFB, Secretary
5829 Parakeet Drive
Burke, VA 22015
.pa.pn3
TABLE OF CONTENTS
Circui Features.......................................4
Vancouver TNC Board Changes............................5
Assembly Instructions..................................7
Installation and Checkout..............................9
Option Settings........................................13
Theory of Operation....................................18
Troubleshooting........................................27
Software Support.......................................30
Parts List.............................................32
Board Layout...........................................33
Schematic Diagram......................................34
.PA CIRCUIT FEATURES
Recently Th Amateu Radi Researc an Developmen
Corporatio (AMRAD) originator o th no popula AX.2 packe
radi protocol develope retrofi boar fo th Vancouve
Termina Nod Controlle board originall develope b Dougla
Lockhart VE7APU Usin th daughte boar (par numbe VDS-1)
system designer ar no free fro th memor constraint o
th origina board Thi translate int bette operatio fo
th Vancouver TNC packe radi enthusiast.
Som o th advantage o th AMRA Vancouve Daughte boar
system are:
* No modifications (jumpers or traces cut) required on the
Vancouver board for normal operation
* No jumper wires to hook between the two boards. All
connections necessary are done via wire-wrap sockets.
* From 8k (using 2716's) to 32k (using 2764's) of EPROM
* From 8k (using 6116's) to 32k (using 8k by 8 chips) of RAM
* Software programmable baud rate generator (using Intel 8253)
Optiona us o time interrupt fo bette softwar control
(requires cutting two traces on the TNC board)
* Position for up to six 16-pin sockets for user kludging
* Position for one 24-pin socket for user kludging
* General kludge area of 11 by 17 tenth-inch spaced holes
* Uses only two additional IC's (other than RAM and EPROM)
* requires no additional power supplies (in fact the minus
five volt supply needed for the 2708's can be eliminated)
* Full documentation available.
* Priced inexpensively at only $25.00 for the bare board.
(which is a Mil-Spec quality board)
To order a VDS-1 board, send $25.00 Plus $2.25 for shipping
(US funds) to:
Technetronics Systems Inc.
ATTN: Charles O. Phillips
6134 Columbia Pike
Falls Church, VA 22041
.pa VANCOUVER TNC BOARD CHANGES
I i no necessar t mak an change t th Vancouve TN
board unless one or more of the following is true:
1. Use of timed interrupts from the 8253 are planned.
2. Th VADC TN boar wa originall assemble usin I
socket wit smal holes Sinc th VDS- interface t
th VADC TN throug wire-wra socket plugge int
fou ke socket (U1 U9 U11 an U18 o th TNC
thes socket mus b capabl o acceptin th large
pin tha wire-wra socket have I thi i no th
case th offendin socket(s mus b replace wit one
that will work before using the VDS-1.
Thes change t th VADC TN ar easil accomplishe i
necessary an wil no affec th operatio o th TN wit o
withou th VDS- installed.
1. Allowing Timed Interrupts From The VDS-1 8253.
Th Inte 825 time chi contain thre indepententl
programmabl timers On o thes i use t provid softwar
contro o th packe channe bau rate Th othe tw ar
availabl t th programme t provid time interrupt t th
TNC Time i optionall wire t th non-maskabl Tra
interrup inpu pi o th 808 CPU whil time i optionall
wire t th maskabl INT interrup pi o th 808 CPU.
Unfortunately th VADC TN ha bot o thes pin shorte
directl t groun (i additio t havin pull-dow resistors)
I orde t us thes input t th CPU the mus firs b
disconnecte fro ground Thi i accomplishe b cuttin tw
trace o th TN board.
Th trac tha mus b cu t allo th Tra interrup i
locate o th botto o th TN board nea pi o th 808
CP (U1) Se Figur 1 Cu 1 fo th exac locatio t plac
th cut.
Figur als show th positio o th trac tha mus b
cu t allo th INT t b used I i locate b pi 1 o U2
the 8255 Parallel Port IC. Cut the board as shown by Cut 2.
.pa VANCOUVER TNC BOARD CHANGES (CONTINUED)
2. TNC Socket Changes
A previousl mentioned certai socket (U1 U9 U11 an
U1 )o th TN boar MUS b abl t accep th large pin use
o wire-wra I sockets
I an o th socket won' accep th wire-wra socke
pins chang th socke i question Thi ca b lo easie
than it sounds, using the following technique.
STEP 1 Remove the IC in the socket to be changed.
STEP 2 Tur th boar ove (componen sid down) an locat th
socke i question Usin solde-sucke (o solde
wick an low-wattag solderin iron carefull remov
a muc o th solde a possibl o eac pin Th mor
solde remove o eac pin th better bu don' spen
lo o tim o eac pin o th trac ma com loos fro
th board Afte al th pin hav bee hi once loo
ove eac pin an tr onc agai t remov an remainin
solder A thi point yo shoul b abl t se throug
th hole a leas mos o th socket pins.
STEP 3 Usin smal pai o needle-nos pliers hea eac pi
wit th solderin iron an wiggl tha pi wit th
pliers Kee wigglin th pi a yo remov th
solderin iro an th pi cool down I th solde wa
sufficientl remove i th las step th pi shoul
sta loos i th hol afte th pi cool down D thi
wit eac pi o th socket Don' worr i al th pin
don' becom loos a first a lon a mos are.
STEP 4 Tur th TN boar over Carefull pr ver smal
blade screwdrive betwee th P boar an th I
socket B carefu no t scratc th boar whil doin
this Remember th socke yo ar removin i t b
throw away s scratc i i necessar rathe tha th
TN board Whil pryin th socke awa fro th board
hea u an socke pin tha ma stil b soldere t th
board B alternatin th hea betwee an pin tha ar
stil soldere an carefull pryin wit th screwdriver
the socket should be walked out of the PC board holes.
STEP 5 Onc th socke ha bee removed g ove th hole o
th TN P boar wit solde wic t remov an solde
left behind.
STEP 6 Plac th ne socke o th TN board an solde i i
place Chec th ne socke t b sur ther ar n
solde bridges I i goo practic t re-instal th
remove I i th ne socke an chec th TN fo prope
operatio befor installin th VDS-1.
.pa VDS-1 BOARD ASSEMBLY
Us th followin step-by-ste instruction t properl
assembl th VDS- daughte board Plac chec mar besid
each step as it is completed.
I orde t us th wire-wra socket a jumper betwee th
tw boards th hole o th daughte boar wer mad large tha
normal Thi ma mak i harde t solde th socket ont th
board Mak sur tha wheneve solderin socket t th daughte
boar ther i sufficien solde betwee th P eyele an th
socke pin Th us o small pointe ti o you solderin
iro wil help.
1. Plac fou 2 pi solder-tai socket i th RA position
(U34 U35 U36 an U37) Solde pin an 1 o eac
socke t hol i i place Whe al fou socket ar i
place solde th remainin pin o th fou sockets Chec
for solder bridges and cold solder joints.
2. Pu th followin solder-tai socket i thei position o
th boar an solde the i place:
A) 16 pin socket at U38.
B) 16 pin socket at U39.
C) 14 pin socket at U40.
D) 14 pin socket at U42.
E) 24 pin socket at U41.
3. Instal eithe fou 2 pi solder-tai sockets o fou 2
pi Zer Insertio Forc (ZIF socket a th fou EPRO
locations U30 U31 U32 an U33 Solde pin an 1 o
eac socke first t hol th socke i place The solde
the remaining pins. Check for solder bridges.
.pa VDS-1 BOARD ASSEMBLY (CONTINUED)
NOTE: Whe installin th wire-wra socket i th nex steps
b sur the ar mounte flus t th board an th pin
ar no crooked I th socket ar no soldere dow
flus t th board th pin wil b crooked causin
alignmen problem durin boar installation.
4. Instal 4 pi wire-wra socke a U1 Notic tha pi
i i th opposit directio a th res o th socket o
th board Carefull solde th wire-wra socke t th
daughter board, making sure there are no solder bridges.
5. Instal 2 pi wire-wra socke a U18 Carefull solde
i t th daughte board makin sur ther ar n solde
bridges Plac piec o tap ove th socket sinc n I
will be installed in this socket.
6. Plac 1 pi wire-wra socke a U9 Not th placemen o
pi 1 Solde al pin ont th daughte board.
7. Instal 1 pi wire-wra socke a U11 notin th
placemen o pi 1 Solde th socke t th board checkin
fo solde bridges Plac piec o tap ove thi socket
since there will be no IC installed in it.
8. Instal th 4 uF 1 vol electrolyti capacito a positio
C (nex t U18 (th valu o thi componen i ver non-
critical) Solde th capacito t th board.
9. Instal th si . u bypas capacitor a C t C o th
board, and solder them in place.
10. Befor installin th VDS-1 mak sur th vol bu i no
shorte t groun a an poin b measurin th resistanc
betwee th vol bu an groun wit volt-ohm-meter I
shoul rea relativel lo a first the slowl ris t
hig resistanc leve (dependin o th valu o C1).
11. I th VDS- passe visua inspection procee t th nex
section of this manual (Installation and Checkout).
.pa INSTALLATION AND CHECKOUT
Thi sectio describe ho t instal th VDS- o th VADC
TN board B carefu no t ben an o th wire-wra pin ou
o alignment o th boar wil no fi a snugl a designed
A wit th VDS- assembl procedure chec of eac ste a i
is completed.
1. I th VDS- i t b altere fro it origina configuratio
a jumpe area JP-5 JP-6 JP-7 o th 8 RA device ar
t b used chec th Optio Setting sectio o thi manua
befor proceedin t th nex ste here Sinc thes jumpe
area ar "normalled o th bac o th VDS-1 th prese
jumpe trace mus b cu BEFOR th VDS- i installe ont
th TN board (except for JP-8).
2. Carefull remov th followin IC fro th VADC TN board
making sure they are not overly handled:
A) U1, 8085, CPU chip.
B) U7, 74LS00, quad nand gate (part of memory decoding).
C) U8, 74LS138, one-of-eight decoder (memory decoder).
D) U9, 74LS138, one-of-eight decoder (port decoder).
E) U11, CD4024, binary counter (baud rate generator).
(be careful with this IC, as it is very sensitive).
F) U15 thru U18, 2708 EPROM memory.
G) U19 thru U26, 2114 RAM memory.
3. Carefull positio th daughte boar ove th mai TN
board makin sur no t ben an o th wire-wra socke
pins Lin u th wire-wra pi sockets startin wit U1
D no pres th pin dow int th socket o th TN boar
yet jus hol the gentl i th socke holes Th daughte
boar ha bee designe ver carefull t mak sur tha th
wire-wra pin lin u properly I ther i proble wit
pi alignment on o mor o th socket ma hav bee
soldere i slightl crooke (thi happene o th VDS-
prototype) I th pin don' alig properly eithe th
socke shoul b re-soldered o th pin ca b ben
slightl usin pai o needle-nos pliers.
.pa INSTALLATION AND CHECKOUT (CONTINUED)
4.Afte U ha bee aligned chec U1 t se i th pin o
th opposit en o th VDS- ar als comin int prope
alignment I the are loo betwee th tw board an mak
sur U i als line u properly Lastly chec U1 a th
to o th boar fo prope pi alignment I ma b
necessar t mov th daughte boar aroun slightl t
accomplis prope alignmen o al pin o al sockets Tak
th extr tim t b sur al pin lin u withou havin t
stres eithe board a thi wil hel i th boar eve
need t b remove an re-installed.
5. Onc al th wire-wra pin lin u properl t th hole i
th socket o th VADC TN board plac th boar o
hard fla surfac an gentl pres o eac wire-wra socke
usin th followin sequenc unti yo fee th pin botto
ou i th TN sockes below
A) Pres th U socke dow first sinc th 4 pi socke
wil b th hardes t alig properly.
B) Next pres th U1 socke down makin sur th res o
th socket ar stil line u properly.
C) Now pres th U socke int it socke o th TN
board.
D) Lastly pres th U1 socke int it socke o th TN
board.
6. Mak sur a leas on o th switche o di switc S- o
th TN boar i ON I doesn' matte which a al th
necessar pin o th U1 socke ar shorte togethe o th
VDS-1.
7.Perfor on fina chec befor installin th IC o th
daughter board, looking over the following:
A) Mak sur al th wire-wra pin ar properl line u i
thei socke holes Mak sur non o th pin ar ben
int wron holes tw pin ar shorte together o
any of the pins are missin thir hole completely.
B) I i goo ide t tak fina readin o th
resistanc betwee th fiv vol buse an ground makin
sur ther ar n direc shorts I ther are remov
th VDS- fro th TNC an chec eac boar separatel
fo shorts.
.pa INSTALLATION AND CHECKOUT (CONTINUED)
7. Install the following Integrated Circuits in their sockets:
A) 8085 CPU at U1.
B) 74LS138 port decoder at U9.
C) 74LS138 EPROM decoder at U38.
D) 74LS138 RAM decoder at U39.
E) CD4024 binary counter at U40.
(Note that this chip seems very sensitive to static)
F) 8253 timer at U41.
G) RAM memory chips (minimum of 2) at U34 to U37.
(minimum 2k parts RAM are U34 at RAM0, U35 at RAM1)
H) EPROM's as necessary in sockets U30 through U33.
(U30 is ROM0, address 0000H)
I) D NO INSTAL U4 A THI TIME I i use onl fo
timed-interrupts an shoul b lef of durin initia
board checkout.
8. I shoul b note tha sinc th memor addres ha bee
altere t allo expande EPRO an RAM an sinc th packe
channe bau rat i no controlle wit softwar rathe tha
S-2 ne sofwar mus b use wheneve usin th VDS-1
Detail o softwar alteration t suppor th VDS- ar
provided in the Software Support section of this manual.
I i goo ide t us monito progra t tes th TN
syste afte installin th VDS-1 Thi way an problem
wit packe radi cod no functionin properl ca b trace
t software rathe tha hardware Ther ar differen
monito program availabl fo th TN baord I yo canno
obtai on fro loca packe enthusiast contac AMRA fo
softwar suppor (eithe 808 typ assembl languag file
unde CP/M o burne EPROMs) Not tha sinc AMRA i
voluntar organization EPROM ma no b immediatel
availabl (i othe words expec th possibilit o sligh
delay)
.pa INSTALLATION AND CHECKOUT (CONTINUED)
Wheneve requestin EPRO suppor fro AMRAD b sur t
includ al necessar informatio suc as:
A) Station Callsign, including SSID.
B) Repeate Callsign (includin SSID's o an repeater t
be used as a default condition during power-up.
C) Ar repeater ar t b defaulte o o of a powe up.
D) Termina configuration Thi include termina speed
parit on/off parit type numbe o sto bits an i
thi TN i t b use a termina o hos computer
Norma operatio i 120 baud n parity on sto bit
and no repeaters.
E) Defaul packe channe bau rat a powe on Thi i
normally set to 1200 baud.
9. Appl powe t th TN board I al goe properly sign-
o messag shoul appea o th terminal I i does
instal th EPROM containin th packe radi code an tr
the out I the functio properly you TN boar i onc
agai read t snatc frame fro th air Tr monitorin a
activ packe channe fo while an connec t someon t
b sur tha al o th packe function ar workin
properly.
10. I yo boar doe no operat properly usin eithe th
monito progra o th packe code se th Troubleshootin
and Theory of Operation sections of this manual.
11. I timed-interrupt ar t b used instal U4 (74LS00) an
apply power. Check for proper interrupt operation.
.pa Option Settings
Th VDS- daughte boar i designe t b flexibl i th
typ an amoun o RA an EPRO i wil support I wil als
allo th timed-interrupt an packe channe bau rat t b
programme unde softwar control Ther ar severa jumpe
area provide o th boar fo alteratio o th standar
configuration Eac o thes options thei associate jumpe
locations, and default settings will be discussed here.
EPROM TYPE DEFAULT TYPE 2732
Th VDS- i designe t us 2716 2732 o 276 typ
EPROMs T alte th VDS- fro th defaul 273 type jumpe
JP-5 must be changed. Use the following steps to alter JP-5:
1. Tur th VDS- boar ove an locat JP- (nex t th
74LS13 EPRO decoder U38) Notic tha ther ar P trace
betwee severa pin o JP- tha ar slightl thinne tha
mos o th other i tha are o th board Usin a Xact
knife carefull cu th followin trace betwee th tw
pin of JP-5 as listed:
A) Cut trace between JP-5 pins 1 and 14.
B) Cut trace between JP-5 pins 2 and 13.
C) Cut trace between JP-5 pins 3 and 12.
D) Cut trace between JP-5 pins 4 and 11.
Instal 1 pi solder-tai socke a JP- an solde i i
place.
Configur 1 pi DI heade fo th prope typ o EPRO
memory chips as follows:
A) 2716 type EPROMs. Wire the following pins together:
Pin 4 to pin 14 (Address line A11 to U38 address A0).
Pin 1 to pin 13 (Address line A12 to U38 address A1).
Pin 2 to pin 12 (Address line A13 to U38 address A2).
Pi 1 t pi 11 (+ volt t 271 pi 23).
B) 2732 type EPROMs. Wire the following pins together:
Pin 1 to pin 14 (Address line A12 to U38 address A0).
Pin 2 to pin 13 (Address line A13 to U38 address A1).
Pin 3 to pin 12 (Address line A14 to U38 address A2).
Pin 4 to pin 11 (Address line A11 to 2732 A11).
.pa OPTION SETTINGS (CONTINUED)
C) 2764 type EPROMs. Wire the following pins together:
Pin 2 to pin 14 (Address line A13 to U38 address A0).
Pin 3 to pin 13 (Address line A14 to U38 address A1).
Pin 5 to pin 12 (Address line A15 to U38 address A2).
Pin 4 to pin 11 (Address line A11 to 2764 A11).
Instal th DI heade i th socke locate a JP-5 Th
resulting memory maps are as follows:
A) 2716 EPROM memory map:
0000H-07FFH U30 (EPROM 0).
0800H-0FFFH U31 (EPROM 1).
1000H-17FFH U32 (EPROM 2).
1800H-1FFFH U33 (EPROM 3).
B) Default 2732 EPROM memory map:
0000H-0FFFH U30 (EPROM 0).
1000H-1FFFH U31 (EPROM 1).
2000H-2FFFH U32 (EPROM 2).
3000H-3FFFH U33 (EPROM 3).
C) 2764 EPROM memory map:
0000H-1FFFH U30 (EPROM 0).
2000H-3FFFH U31 (EPROM 1).
4000H-5FFFH U32 (EPROM 2).
6000H-7FFFH U33 (EPROM 3).
RAM TYPE DEFAULT: 6116 TYPE
I th RA memor chip use ar t b change fro th
default 6116 type devices, use the following procedure:
1. Tur th VDS- boar ove t th botto o th boar
(COPYRIGH 198 notice an locat JP- (nex t U39)
Locate and cut the following traces at JP-6:
A) Cut trace between JP-6 pins 1 and 14.
B) Cut trace between JP-6 pins 2 and 13.
C) Cut trace between JP-6 pins 3 and 12.
D) Cut trace between JP-6 pins 6 and 9.
.pa OPTION SETTINGS (CONTINUED)
2. Instal 1 pi solder-tai socke a locatio JP-6 an
solder it in place.
3. Wir DI heade fo th typ o RA memor t b use
according to the following:
A) If 6116 type (2k by 8) devices are being used:
1) Wire pin 1 to pin 14 (Address line A11 to U39 A0).
2) Wire pin 2 to pin 13 (Address line A12 to U39 A1).
3) Wire pin 3 to pin 12 (Address line A13 to U39 A2).
4) Wire pin 6 to pin 9 (WR* to 6116 WR* pin).
B) If 6264 or 2186 RAM chips (8k by 8) are being used:
1) Wire pin 3 to pin 14 (Address line A13 to U39 A0).
2) Wire pin 4 to pin 13 (Address line A14 to U39 A1).
3) Wire pin 5 to pin 12 (Address line A15 to U39 A2).
4) Wire pin 1 to pin 9 (Address line A11 to RAM A11).
4. Place the appropriate DIP header into the socket at JP-6.
5. I 218 RA chip ar bein used als instal jumper a
location JP-9 JP-10 JP-11 an JP-1 o th BOTTO o th
VDS- board Th 218 typ RA chip ar actuall psuedo-
stati devices whic ma requir synchronizatio wit th
808 CPU Thes jumper hoo th 218 read line t th
808 read pin allowin memor synchronization.
6. The resulting memory map for the RAM memory is:
A) For 6116 type (2k by 8) devices:
8000H-87FFH U34 (RAM 0)
8800H-8FFFH U35 (RAM 1)
9000H-97FFH U36 (RAM 2)
9800H-9FFFH U37 (RAM 3)
B) For 6264 and 2186 type (8k by 8) devices:
8000H-9FFFH U34 (RAM 0)
A000H-BFFFH U35 (RAM 1)
C000H-DFFFH U36 (RAM 2)
E000H-FFFFH U37 (RAM 3)
.pa OPTION SETTINGS (CONTINUED)
TIMER OPTIONS
Ther ar thre independent softwar programmabl timer
i th 825 time IC Th onl time tha mus b use i
suppor o th VDS- daughte boar i time 0 whic i use t
generat th bau rat o th packe channel Fo prope
operation th 825 inpu cloc canno excee MHz
Unfortunately th Vancouve TN maste cloc frequenc i 2.457
MHz Thi mean th maste cloc mus b divide befor sendin
i t an o th cloc input o th 8253
I addition sinc th maximu diviso o sixtee bi
counte i 65,53 an th inpu cloc woul no b 1.228 MHz
th slowes resultin interrupt woul b abou 1 pe second
wit n tri contro i tha rang (nex slowes woul b doubl
that o 3 interrupts/sec.) Ther need t b bette wa o
trimmin th numbe i interrupt pe second i timed-interrupt
ar t b use effectively Thi i accomplishe wit U4 an
JP-7.
Th output o U4 (CD4024 ar wire t pin 1 an thr
o JP-7 Eac o thes pin i successiv divide-by-tw o
th previou pin' frequency Th followin pin a JP- hav
th accompanyin frequencies an ar normall jumpere t th
followin inpu clock o U41:
Pin 1 1.2288 MHz (Baud Rate Generator input)
Pin 3 6144 KHz (Trap timer, INTR timer inputs)
Pin 4 3072 KHz
Pin 5 1536 KHz
Pin 6 768 KHz
Pin 7 384 KHz
Pi 1 o JP- i normall jumpere t th inpu cloc o
time i U41 Thi provide a acceptabl cloc frequenc t
time 0 whic i use a th bau rat generato fo th packe
channel Othe output coul b use i necessary bu th nee
fo thi i no anticipated.
Pi 1 o JP- i th inpu cloc t time o U41 Time
optionall drive th Tra interrup inpu t th 808 CPU
Th tra interrup i non-maskable s ther i n wa o
disablin thes interrupt i th hardwar i enabled Usin th
secon outpu o U4 usuall give enoug contro o th
resulting interrupt rate.
.pa OPTION SETTINGS (CONTINUED)
Pi 1 o JP- i th inpu cloc t time 2 an i als
normall wire t th secon outpu o U40 Time optionall
drive th INT interrup inpu t th 808 CPU Th INT pi
generate maskabl interrupt whic allow th softwar t
selectivel disabl thi interrupt A wit th Tra interrup
above th secon outpu o U4 usuall give enoug contro ove
the frequency of INTR interrupts.
I an o th timin parameter se b JP- ar t b
altered i i recommende tha socke b installe a JP-7
an DI header b use t chang th defaul values Thi i
accomplished as follows:
1. Tur th VDS- boar ove an locat jumoe JP- (nex t th
U4 socket) Carefull cu th followin traces:
A) Pin 1 to pin 14
B) Pin 2 to pin 13
C) Pin 2 to pin 12
2. Plac 1 pi solder-tai socke a JP-7 an solde i i
place.
3. Wire a DIP header as necessary for the alterations requied.
4. Plac th DI heade i th socke a JP-7 an tes ou th
changes.
TIMED INTERRUPT ENABLES
Th outpu o th tw timer tha ar capab o generatin
interrupt ar normall disable by no installin U4 (74LS00)
I time interrupt ar t b used U4 shoul b installed
Jumpe JP- i use t selectivel enabl onl on o th othe
o th time interrupts a necessary JP- i normall jumpere
o fo bot interrupts othe configuration ca b mad b
cutting the traces ot the TOP of the board at JP-8 as follows:
1. Cut trace between pins 1 and 4 to disable Trap interrupts.
2. Cut trace between pins 2 and 3 to disable INTR interrupts.
Thes trace wer place o th TO o th VDS- boar t
allow easy access to them.
Kee i min tha th timer MUS b properl programme
befor time interrupt ar enabled otherwis imprope operatio
wil result Not tha timer an shoul b programme fo
puls operation rathe tha squar wave sinc th interrupt
are level sensitive.
.pa THEORY OF OPERATION
I orde t bette understan ho th VDS- daughte boar
interface wit th VADC TNC w wil firs delv int th VADC
TN itself Sinc th origina manua supplie wit th VADC
TN di no contai theor o operatio section w wil tr t
fill in that gap to some degree here.
TNC HARDWARE OVERVIEW
Th VADC TN i actuall singl boar compute dedicate
t changin dat betwee tw differen transmissio format
(usuall asynchronou ASCI an HDL typ frames) Lik mos
othe singl boar computers th TN ha Centra Processin
Uni (CPU tha act a th brain o th computer EPRO memor
tha contain th instruction fo th CPU RA memor t hol
dat an contro informatio temporarily an som inpu an
outpu (I/O device wit whic t communicat t th outsid
world Se Figur 2 fo bloc diagra o th VADC TNC.
.pa THEORY OF OPERATION (CONTINUED)
CPU AND AND CPU SUPPORT CIRCUITRY
Th VADC TN boar use th Inte 808 CP chip Th 808
i a improve versio o th popula 8080 I i softwar
compatibl wit th 8080 whic mean program writte fo th
808 wil usuall ru fin o a 8085
Th 808 CP ha built-i cloc generator O th VADC
TN board 4.915 MH crysta i use t determin th
cloc rate Thi frequenc wa probabl chose becaus i i
multipl o mos o th standar bau rates Th interna
oscillato divide thi frequenc i half resultin i a actua
cloc rat o 2.457 MH (bot interna t th 808 an th res
of the board).
Th 808 use multiplexe dat an lo hal addres bus
Thi mean tha th dat an lowe portio o th addresse shar
th sam se o pin o th 8085 I orde t accomplis this
th 808 send specia signa out calle Addres Latc Enable
o ALE wheneve addres informatio i o th AD0-AD lines O
th TN board a eight-bi latc (U6 74LS373 i use t latc
an hol th lo addres wheneve tol t b th AL pi fro th
8085.
Th 808 CP ha severa pin tha ca b use t directl
contro th CP actions Som o thes ar th sam a th 8080
whil other ar ne t th 8085.
Th rese pi cause th CP t sto whateve i wa doing
an immediatel g t th beginnin o memory Thi pi shoul
b hooke t pushbutto typ switc s tha th operato ca
recover the board in case of a failure in program control.
Ther ar severa interrup pin o th 8085 Interrupt
ar jus wha th nam implies i th associate pi i
asserted th CP wil temporaril suspen whateve i i doing
an d somethin els (whateve th interrup requested o th
CP i programme t do) Som interrupt ar controllabl
(maskable a t whethe th CP wil acknowledg an hono them
whil other th CP ha n contro ove (non-maskable) i whic
cas th CP MUS hono th interrupt Sinc ther ar severa
differen interrupts an eac ma occu a an time eac on i
assigne a orde o precedence Th interrupt o th TN baor
wil b discusse i increasin orde o importance.
.pa THEORY OF OPERATION (CONTINUED)
Th lowes priorit interrup i th INT pi o th 808
(pi 10) Thi pi i leve sensitive hig indicate
reques fo interrupt I i maskable allowin th CP t
ignor an INT requests I a INT interrup i allowe b th
CPU th CP wil indicat thi b assertin th Interrup
Acknowledg pi (INTA* low Th requestin devic ca the
forc a instructio (usuall cal o restart ont th dat
bus an th CP wil excut tha instruction Th VADC TN
normall ha thi pi tie low disablin th INT function.
Th nex grou o interrupt ar th RS pins Thes pin
hav highe priorit tha th INT pin ar maskabl b th
CPU bu the operat slightl differently Whe on o th RS
pin i asserted i cause th CP t g t specifi locatio
i memory an execut instruction startin a tha locatio a
i cal t tha locatio wa requested Th memor locatio
called th typ o signa used th orde o priority an
sourc o th reques o th TN boar ar show below.
Interrupt Memory Signal Priority Interrupt Source
--------------------------------------------------------
RST 5.5 002CH High Low User Interface
RST 6.5 0034H High Middle U10 (8273) TxINT
RST 7.5 003CH Pulse High U10 (8273) RxINT
Th highes priorit interrup o th 808 i th Tra
interrup (pi 6) I i non-maskable an generate restar
t memor locatio 0024H I i bot edg an leve sentitive
Th TN boar ha thi pi tie low disablin th Tra
interrupt.
Th 808 CP als generate som timin signal neede fo
proper computer operation. These include:
IO/M* Low for memory request, high for input/output
RD* Low indicated a read function from memory or I/O
WR* Low indicates a write function to memory or I/O
RESET OUT High indicates the CPU is being reset.
Ther i als pi calle Ready whic i use t
synchroniz CP operatio wit slowe memory Thi pi i no
used on the original VADCG TNC board.
.pa THEORY OF OPERATION (CONTINUED)
TNC EPROM MEMORY
I orde fo th TN boar t functio properly th CP
mus b tol wha t d b program Thi progra i hel i
Erasable-Programmable-Read-Only-Memor (EPROM) Th TN use
fou 270 typ EPRO chips eac o whic hold 102 byte o
program fo tota o 409 byte (4k o progra memory
Ther i memor decode circui mad u o U (74LS00 an
U (74LS138 tha determine wher i th CP memor th EPRO
(an RAM sinc th sam decode i use fo both i t reside
Th memor ma fo a unmodifie TN boar is:
0000H-03FFH U15 (EPROM 0)
0400H-07FFH U16 (EPROM 1)
0800H-0BFFH U17 (EPROM 2)
0C00H-0FFFH U18 (EPROM 3)
1000H-13FFH U19, U20 (RAM 0)
1400H-17FFH U21, U22 (RAM 1)
1800H-1BFFH U23, U24 (RAM 2)
1C00H-1FFFH U25, U26 (RAM 3)
2000H-FFFFH Unused, copies of above map
Th 74LS0 (U7 i use wit th addres decoder 74LS13
(U8) t decod memor read-onl cycle fo th EPROM an memor
read/write cycles for the RAM memory.
Not tha th EPRO chip ar i th opposit sequenc tha
on woul assume tha i EPRO i th right-most no th
left-mos EPROM Th 270 EPROM requir +5V -5V an +12 t
operate properly.
TNC RAM MEMORY
Fo th TN t functio properly i additio t EPRO
memor t stor th program ther mus als b som amoun o
temporar memor tha wil b use t stor th dat i need t
process Th TN boar use 211 typ RA chips whic ar 102
b bits Tw o thes chip ar neede t stor complet
bit wort o data Ther i roo fo fou bank o thes chips
fo tota o 409 byte o dat storage Th RA memor share
th sam memor decode circuitr wit th EPROM an i
discussed above.
Sinc th 808 CP use bidirectiona dat bus th IN/OU
pin o th 211 chip ar connecte directl t th CP dat
bus.
.pa THEORY OF OPERATION (CONTINUED)
TNC INPUT/OUTPUT
I orde fo th TN boar t function i mus ge dat
fro th outsid worl t process an the sen th processe
dat bac t th outsid worl whe done Thi functio i
provide b th inpu an outpu device o th TN board Ther
ar tw differen "channels fo dat t transfe betwee th TN
an device connecte t it Th firs i th "use interface"
an th secon i th lin o packe channel Eac on o thes
channel i connecte t th TN CP throug specia ICs whic
occup certai por location i th CP por addres space
Eac o thes IC i als capabl o generatin interrupt t th
CPU when it needs to be serviced.
Th I/ port use ar decode b U9 74LS138 I decode
onl I/ por addresses whic ar mappe a follows:
00H-07H U3 8250 Serial I/O Port (User Interface)
08H-0FH U2 8255 Parallel I/O Port (User Interface-Optional)
10H-17H U10 8273 HDLC Protocol Main Ports (Packet Channel)
18H-1FH U10 8273 HDLC Protocol TX Data Port (Packet Channel)
20H-27H U10 8273 HDLC Protocol RX Data Port (Packet Channel)
28H-FFH Unused.
Th use interface t th VADC TN boar eithe throug
seria (RS-23 o curren loop o paralle port Mos o th
softwar suppor fo th VADC TN use onl th seria interfac
option an the onl a ASCII RS-23 typ o seria interface
I woul hav bee nic t hav bee abl t us bot th seria
an paralle chip simultaneously bu sinc the shar quit
fe o th sam DB-2 connecto pins thi i impractica withou
cuttin severa traces an addin anothe connector.
Serial User Interface
Th seria use interfac use a 825 Asynchronou
Communication Elemen (ACE) Thi chi ha bot UAR an
bau rat generato buil int it I additio t seria dat
line i an out i als provide som o th handshakin line
typicall foun i a RS-23 interfac (DSR DTR RTS CTS DCD
an RI) Th TN boar ha RS-23 drive chip o i t
optionall mak thes signal eithe TT o RS-23 voltag
levels Sinc th AC chi i complicate device severa I/
port ar assigne t i fo prope programmin an operation
.pa THEORY OF OPERATION (CONTINUED)
These ports are designated as follows:
Port 00 Transmit/Receive Data Buffer Registers.
Port 01 Interrupt Enable Register (Write Only).
Port 02 Interrupt Identification Register (Read Only).
Port 03 Line Control Register (UART Functions).
Port 04 Modem Control Register.
Port 05 Line Status Register (UART Status).
Port 06 Modem Status Register.
Port 07 Baud Rate Divisor Latch Registers.
Parallel User Interface
Th paralle use interfac use a 825 Programmabl
Periphera Interfac (PPI) Thi devic ha 2 line o paralle
data eac o whic i programmabl t b eithe input o
outputs I addition som o thes line becom handshakin
line whe programme properly allowin ful 1 bi paralle
Input/Output system with complete strobing and acknowledgements.
Th 2 line o th 825 ar organize a thre group o
line (group A B an C) wit thir grou (C bein furthe
divide int tw 4-bi subgroups Th programmin o thi chi
i beyon th scop o thi manual howeve th Por ma fo thi
device on the TNC is as follows:
Port 08H Port A Data Bus.
Port 09H Port B Data Bus
Port 0AH Port C Data Bus.
Port 0BH PPI Control Port.
Ports 0CH-0FH will be in same as above.
Sinc virtuall n on i usin th paralle use interface
these locations are generally ignored.
Packet Channel Interface
Th packe channe interfac i handle b a Inte 827
HDL Protoco Controlle chip Th 827 i ver complicate
inside i tha i automaticall handle lo o th HDL
protoco functions suc a cloc recovery NRZ
encoding/decoding zer bi insertion/removal an frame-check-
sequenc (CRC generation/checking Sinc th packe channe
send HDL frame i synchronou mod (n star o sto bits
onc thi chi start sendin fram o data i mus continu
unti al th dat o tha fram i sent Ther ca b n
startin an stoppin i th middl o sendin frame Thi
mean th 827 mus b capabl o gettin th attentio o th
TN CP quickl wheneve fram i bein sen o received
.pa THEORY OF OPERATION (CONTINUED)
Becaus o this th 827 use th highes interrupt o th
TN board Th transmi an receiv dat register als us
separat port tha th res o th 8273 Th por ma o th
827 is:
10H 8273 Main Command/Status Register.
11H 8273 Parameter/Result Register.
12H 8273 Reset/Tx Interrupt Result Register.
13H 8273 Rx Interrupt Result Register.
14H-17H Same registers as above.
18H-1FH 8273 Transmit Data Register.
20H-27H 8273 Receive Data Register.
Th 827 doe no hav a interna bau rat generator s
a externa divide mus b used U11 CD402 seve stag
binar counte i use t divid dow th 2.4576MH cloc t th
frequencie necessar fo th 827 t work Th 827 ha
digita phase-lock-loo (DPLL tha i use t recove th dat
timin o th packe channel Thi DPL need X3 cloc t
functio properly Th output o U1 ar sen t switc S2
Onl on o th switche o S shoul b o a an give time
Th output o U1 provid fo bau rate fro 38,40 bau t 60
baud.
Th 827 provide mos o th primar signal use i a RS-
23 interfac (TXD RXD CTS RTS an DCD) I addition ther
ar tw eac use programmabl inpu an outpu pins Th VADC
TN feed thes signal t 1 pi DI socke a J4 Th othe
hal o J lead t th RS-23 leve converte ICs whic the
lead to the packet channel DB-25, J2.
Daughter Board Theory
Th VDS- daughte boar wa designe t replac th memor
o th Vancouve TN board I addition i provide softwar
contro ove th packe channe bau rate an th optio o tim
generate interrupts.
Th VDS- interface t th Vancouve TN throug fou wire-
wra socket tha plu int ke socket o th TN board Th
firs one i at th CP socket U1 Th 808 CP no plug int
th wire-wra socke o th daughte board Usin thi socket
severa o th ke signal t an fro th CP ca b easil
obtaine.
.pa THEORY OF OPERATION (CONTINUED)
Th nex socke tha plug int th TN i a U18 Thi
use t b on o th 270 EPRO sockets Thi socke i use t
recove th latche low-orde addres bu fro th latc (U6 o
th Vancouve TNC I wa possibl t ad anothe latc o th
daughte board bu tha woul hav increase loadin o th dat
bu unnecessarily I addition pluggin int U1 provide
structura suppor fo th VDS-1 Sinc th socke a U1 i
used only as a jumper, there is not an IC that plugs into U18.
Th thir wire-wra socke betwee th tw board i a U9
th I/ por decoder Thi socke i use t ge th additiona
por decode outpu fo th 825 time I a U41 U4 use port
28 t 2FH Th I tha wa plugge int U o th TN no plug
into the daughter board U9 instead.
Th fourt wire-wra socke i a U11 Thi positio use
t hav th CD402 bau rat generato plugge int it Sinc
th bau rat i no generate b U41 ther i n I plugge
int th U1 socke o th daughte board Not tha al th ol
outpu pin o th CD402 ar no shorte together i doesn'
matte whic switc a S i closed a lon a a leas on is.
VDS-1 EPROM Memory
Th VDS- boar ha fou socket fo EPRO use Th type
o EPROM acceptabl b th VDS- ar 2716 2732 o 2764 Al
fou EPROM mus b o th sam type ne EPRO addres
decode i use o th daughte boar a U38 Th addres input
t U3 com fro jumpe JP-5 JP- i pre-wire fo 273 typ
EPRO decoding I EPROM othe tha 2732' ar t b used th
trace o th bac o th VDS- mus b cu befor usin JP-5
See the Option Settings section for further details.
Not tha al thre type o EPROM usabl o th VDS- ru
o +5 only s th othe tw voltage use b th 270 EPROM
ar no neede fo EPRO use Th -5 i n longe neede a
all s i ca b eliminated Th +12 i use b th RS-23
interfaces s i i stil needed Anothe advantag o gettin
ri o th 2708' i tha th newe type o EPROM ru a
higher speed, reducing the potential of timing problems.
.pa THEORY OF OPERATION (CONTINUED)
VDS-1 RAM Circuitry
separat RA memor decode (U39 74LS138 i no use
o th VDS-1 Thi allow th RA chi siz t b differen tha
th EPROM allowin greate syste flexibility Lik th EPRO
decoder th RA decode addres input com fro jumpe (JP-
6) Thi jumpe i pre-wire fo 611 typ devices Optionally
626 o 218 typ (8 b 8 device ca b used i JP- i
altered Sinc th 218 i psuedo-stati devic (i i reall
dynamic bu al suppor circuitr i insid th chip) i need
t tel th CP wheneve i i no ready Thi i wh th
jumper JP- thr JP-1 ar needed The allo th RA chip t
tel th CP whe the ar no read yet an th CP add wai
state unti th RA chip ar ready.
VDS-1 Timing Circuitry
On o th problem wit th origina Vancouve TN i tha
th use mus chang switche t alte th bau rat o th
packe channel I addition th slowes spee th TN boar
run withou modificatio i 60 baud Thi i stil to fas
fo H packe operatio a th moment Th VDS- remove thi
proble b replacin th CD402 binar counte an S wit
programmabl time I (U41 a 8253) Th 825 ha thre
separat programmabl timers on o whic i use t creat th
cloc fo th 827 Protoco Controller Unfortunately th 825
ca onl handl inpu cloc speed u t MHz Th TN board'
cloc i divide b tw b U4 o th daughte boar (th no
famou CD4024 whic i the sen t th 825 time cloc
input Th outpu o time i the sen t th wire-wra
socket at U11, which feeds it to the TNC board.
secon outpu o th CD402 i use t driv th 825
inpu cloc fo timer an 2 Thes timer ar optionall use
t driv th tra (non-maskable an INT (maskable interrup
input t th 808 CPU Sinc th output o th timer ar
activ low the mus b inverte befor sendin the t th CPU
Thi inversio i accomplishe b U42 74LS00 Thi I wa
lef ove fro th origina Vancouve TN memor decoder I
time interrupt ar no bein used the shoul b disable b
removing U42.
Jumpe JP- i provide t allo th use t alte th
standar inpu cloc rate t th 825 timer I i no
anticipate tha thes nee t b changed s JP- i normall
not altered.
Not tha i timer o ar use t generat time
interrupts the mus b programme fo shor duratio pulse
sinc th TRA an INT interrupt ar leve sensitive an wil
continue to interrupt as long as the inputs are high.
.pa TROUBLESHOOTING
Sinc th Vancouve TN i complet microcompute system
i ca b ver difficul t correc problem tha ma arise I
ther i problem us th followin step a guidelin t
troubleshoo th TN system I i helpfu t hav anothe TN
board available for comparing, and also for chip swapping.
Certai o th followin step ca b ignore i tha par
o th boar seem t b functioning If fo example th boar
work wit th terminal bu wil no transmi o receiv ove
th packe channel th whol TN i no defective bu rathe
jus th HDL controlle o it suppor circuitry Th followin
step ar mor t hel whe th whol TN seem t b out-to-
lunch.
Step 1. Overall Tests
A.Mak sur tha al chip o th TN ar positione properly
Th TN boar ha severa chip i differen orientations s
i i eas t pu chi i backwards Als mak sur tha
non o th pin o th chip i ben unde rathe tha i
th socke hole Thi ca b don b lookin carefull dow
th en o eac socket I pi i ben under remov th
chip, bend the pin back, and re-install the chip.
B.I th TN function properl unti i trie t transmit
the eithe send stead tone o continua flag (th
eterna fram syndrome) replac th CD4024 an tr again
Thi chi i EXTREMEL sensitiv t static an i th numbe
one cause of TNC malfunctions that AMRAD has encountered.
C. Chec th powe suppl lines bot wit mete AN scope
Thre termina regulator hav habi o goin int
oscillation, which won't show up on a meter.
D.Chec th TN syste wit monito RO tha i know t
work Sometime EPROM forge bi her o there causin
strange results.
E. Doubl chec th jumper o bot boards I i no
immediatel obviou wha th prope jumpe configuratio o
th Vancouve TN boar should be i al cases.
F.Remov th daughte boar an re-instal th IC remove fro
th TNC Tr bringin u th TN withou th daughte boar
t identif wher th proble is preferabl usin monito
progra i 270 an RA a 1000H-1FFFH I th TN
functions normally, proceed to step 3, VDS-1 Troubleshooting.
.pa TROUBLESHOOTING (CONTINUED)
Step 2. Vancouver Board Troubleshooting
A. Appl powe t th TN board Usin scope chec pi 3 o
U fo 2.457 MH clock Th actua frequenc i no
importan a thi time a lon a i i nice clea squar
wave I not tr installin coupl 20p capacitor fro
U pin an t ground Sometime th 808 need thes
capacitor t functio properly I tha doesn' correc th
problem replac th 808 (U1) an the th crysta i stil
no clock.
B.Pus th Rese button A lon a th butto i hel down
U pi 3 shoul b low an U pi shoul b high Th
following should also be true as long as reset is held down:
1) Data lines (pins 12-19) should be high.
2) Address lines (pins 21-28) should be 1V. or less.
3) Pins 31, 32, and 35 should be held high.
4) Pins 30, 34, 6, and 10 should be low.
5) Pins 7, 8, and 9 should be low, depending on other chips.
C.Consul you schemati i on o thes pin i no a th
proper level, and look over the TNC board for shorts.
D. Releas th Rese button U pi 3 shoul no g high an
pi shoul g low Th followin shoul als b checke
(sinc th addres an dat buse ar no buffered thes
signal wil no b idealy shape pulses):
1) Data lines should have alternating high-low pulses.
2) Address lines should have alternating ihgh-low pulses.
3) Chec th outpu pin o th addres latc (U6 t mak
sure it is latching the low-half address properly.
4) Mak sur th pin 30 31 32 an 3 als hav pulse
whe the are supposed to.
5) Typ character o th consol (assumin seria inter
face an loo fo U pi (RST5.5 t g hig o eac
keystroke.
E.Chec fo active-lo transition o th chi selec pin o
a leas th lo EPRO (U1 pi 20) Ther shoul als b
intermitten transition o th RA chi selec lines
depending on the program being run.
F. I nothin obviou ha be foun a thi point usuall th
nex ste i t star swappin chip betwee functiona TN
an th defectiv board I al th chip hav bee changed
an th boar stil fail t operate i i tim t chec th
boar wit mete fo short o ba sockets
.pa TROUBLESHOOTING (CONTINUED)
Step 3. Daughter Board Troubleshooting
Not tha al pi number fo EPRO an RA chip mentione
belo (excep fo U18 ar assumin 2 pi sockets sinc tha i
wha th daughte boar i laye ou for Tak thi int accoun
when testing 24 pin devices in the 28 pin sockets.
A. Mos problem associate wit th daughte boar hav t d
wit th interconnection betwee i an th TN board Mak
sur onc agai tha al socket ar soldere properly an
that all the pins line up in the proper holes.
B.Remov U42 i installed Thi wil mak sur n spuriou
interrupt ar bein generate b th 825 timers U4
shoul b installe ONL i softwar i include t suppor
timed interrupts.
C.Mak sur tha al th jumper o th daughte boar ar
correc fo th typ o memor bein used Th VDS- i
normall jumpere fo 273 EPROMs an 611 RAMs Se th
Options Setting section for more information.
D. Follo throug D i Ste above Perfor th test firs
o th 808 itself the o th botto o th TN board' U
socke t mak sur al th signal ar makin i throug th
jumpers ok.
E.Chec U1 pin t t mak sur al bit o th low-orde
address bus are getting from the TNC to the daughter board.
F. Chec th outpu o th addres decoders A minimum U30
pi 2 (EPRO chi select shoul b periodicall pulsin
low I addition U3 pi 2 shoul als b pulsin low
depending on the software being used.
G. A wit th TN boar itself th easies metho t procee
a thi poin i t swa al IC o th daughte boar wit
on tha i functiona (i migh b goo t tr th othe
daughte boar first) I problem persist carefull g
over the daughter board for shorts of bad solder joints.
.pa SOFTWARE SUPPORT
Ther ar fe modification tha mus b mad t an
softwar befor runnin i o Vancouve TN wit th VDS-
installed Thes hav t d wit large EPRO space relocate
an large RAM softwar contro o th packe channe speed an
optionally timed interrupts.
EPROM SUPPORT
Actually n change nee t b mad fo th EPRO spac
itself bu th additiona EPRO spac mean tha al RA
location equates need to be changed.
RAM SUPPORT
Mos o th program writte fo th Vancouve TN us tw
equate fo th RAM on fo th beginnin an th othe en o
RA memory Al othe reference t RA memor location ar
mad base o thes tw equates Whe usin th VDS-1 al RA
start a locatio 8000H Usin fou 611 typ RA chips RA
wil en a 9FFFH Thi mean th tw equate ar no a
follows:
LORAM EQU 8000H ; Start of RAM memory
HIRAM EQU 9FFFH ; End of RAM memory
I addition tw othe equate mus b change i th
LIPM.AS fil t mak i wor properly Th orde o thes
equates is now reversed, and they MUST be in this sequence:
LBALEN EQU (HIRAM-LBA)/2 ; LENGTH OF LINE BUFFER AREA
LBAEND EQU (LBA+LBALEN) ; NEXT BYTE AFTER LINE BUFFER
TIMER SUPPORT
Sinc th packe channe bau rat i no controlle b
software som softwar mus b provide t se th packe speed
I addition th time mus b initialize befor an spee ca
b selected Th mos rudimentar for o cod t d thes
functions at 1200 baud is as follows:
CTR0 EQU 28H ; COUNTER 0 PORT
CTR1 EQU 29H ; COUNTER 1 PORT
CTR2 EQU 2AH ; COUNTER 2 PORT
CTRPRM EQU 2BH ; COUNTER PARAMETER PORT
CTRIN: MVI A,36H ; CTR0, SQUARE WAVE, BINARY MODE
OUT CTRPRM ; SEND IT TO THE PARAMETER PORT
MVI A,20H ; LOW HALF DIVIDER FOR 1200 BAUD
OUT CTR0 ; SEND LOW HALF TO COUNTER 0
MVI A,0 ; HIGH HALF DIVIDER 0
OUT CTR0 ; AND SEND IT TO COUNTER 0
.pa SOFTWARE SUPPORT (CONTINUED)
Th followin i som informatio o programmin th 825
chip I i give i assembl forma t ai i installin i i
software.
CNTR02 EQU 80H ; SELECT COUNTER 2 FOR PROGRAMMING
CNTR01 EQU 40H ; SELECT COUNTER 1 FOR PROGRAMMING
CNTR00 EQU 00H ; SELECT COUNTER 0 FOR PROGRAMMING
RDLDBH EQU 30H ; READ/LOAD LOW BYTE FIRST, THEN HIGH
; OF DIVIDER IN COUNTER SPECIFIED
RDLDHI EQU 20H ; READ/LOAD HIGH BYTE ONLY OF DIVIDER
RDLDLO EQU 10H ; READ/LOAD LOW BYTE ONLY OF DIVIDER
CNTLAT EQU 00H ; LATCH THE COUNTER AT PRESENT COUNT
MODE05 EQU 0AH ; MODE 5 (HWARE TRIGGERED STROBE)
MODE04 EQU 08H ; MODE 4 (SWARE TRIGGERED STROBE)
MODE03 EQU 06H ; MODE 3 (SQUARE WAVE GENERATOR)
MODE02 EQU 04H ; MODE 2 (PULSE RATE GENERATOR)
MODE01 EQU 02H ; MODE 1 (PROGRAMMABLE ONE-SHOT)
MODE00 EQU 00H ; MODE 0 (INTERRUPT ON TERMINAL CNT)
BCDCNT EQU 01H ; BCD COUNTER MODE (4 DECADES)
BINCNT EQU 00H ; BINARY MODE (16 BITS).
I shoul b note tha eac counte i programme vi th
contro port an tha th actua counte port ar use onl fo
loading or reading the count of the timer.
Consul th Inte 825 dat sheet fo mor informatio o
programming the 8253.
Th nex tabl contain th BINAR divide t loa int th
8253 timer 0 for most common baud rates.
-------------------------------------------------------
! SPEED ! Low Half Divider ! High Half Divider !
! ------------!-------------------!-------------------!
! 9600 ! 04H ! 00 !
! 4800 ! 08H ! 00 !
! 2400 ! 10H ! 00 !
! 1200 ! 20H ! 00 !
! 600 ! 40H ! 00 !
! 300 ! 80H ! 00 !
! 150 ! 00H ! 01H !
! 75 ! 00H ! 02H !
-------------------------------------------------------
.PA VDS-1 PARTS LIST
Th followin i lis o part necessar fo th
construction of the AMRAD VDS-1 Daughter Board.
QUANTITY PART NUMBER DESCRIPTION
---------------------------------------------------------------
1 VDS-1 AMRAD Daughter PC Board.
1 74LS138 1 of 8 Decoder IC
1 8253 Programmable Interval Timer IC
1-4 2716,2732,2764 EPROM Memory IC (depending on size)
1-4 6116,6264,2186 RAM Memory IC (depending on size)
1 40 Pin Wire-Wrap IC Socket
1 24 Pin Wire-Wrap IC Socket
1 16 Pin Wire-Wrap IC Socket
1 14 Pin Wire-Wrap IC Socket
8 28 Pin Solder-Tail IC Socket (optionally 4 Solder-Tail
an ZI socket fo EPROMs)
1 24 Pin Solder-Tail IC Socket
2 16 Pin Solder-Tail IC Socket
2 14 Pin Solder-Tail IC Socket
3 14 Pin Solder-Tail IC Socket (Options)
3 14 Pin DIP Headers (Options)
1 47uF 10V Electrolytic Capacitor (value not critical)
6 .1uF 50V Disc Capacitor
.pa--
======================================================================
signed: Rod Hart (wa3mez)
Chesapeake & Potomac Tel. Co.
Bell Atlantic Inc.
Silver Spring, Md.
gamma!cp1!hart - umcp-cs!cp1!hart - aplvax!cp1!hart
======================================================================WMartin@SIMTEL20.ARPA (08/10/84)
From: William G. Martin <WMartin@SIMTEL20.ARPA> This message arrived over here on the ARPANET side with about 1/4th of the letters in the the text missing, in seemingly random patterns. Does anyone know why? Will -------
Denber.wbst@XEROX.ARPA (08/10/84)
letters on all the words. - Michel
W8SDZ%SIMTEL20@sri-unix.UUCP (08/11/84)
From: Keith Petersen <W8SDZ@SIMTEL20> Rod, the vadg daughter file looked like it may have come from WordStar and had some high-order bits turned on, which the uucp mailer didn't know what to do with. Rather than re-mail that long file to the whole net, please send it (after stripping the high-order bits) to my BRL-BMD address and I'll put it in MICRO:<CPM.HAMRADIO> here at SIMTEL20 so others can get it with FTP. I'll post a message to Info-Hams when it's available here. --73, Keith
Cherry.es@XEROX.ARPA (08/13/84)
Keith, Please forward a copy to the Xerox.Arpa distribution as most of us do not have access to Micro:<cpm.hamradio>. Thanks. Bob/wa0tzm