piety@hplabs.UUCP (Bob Piety ) (12/06/84)
A friend has a Uniden EX-3100 cordless telephone that has a "CMOS latchup" problem. Every couple of days, the base unit quits working, necessitating unplugging the power and plugging it back in to restore proper operation. I'm guessing that it is caused by his archaic telephone switching office's transients & glitches. He has exchanged the unit-- same results. Has anyone else had similar problems with this or any other model cordless telephone? What have you done to solve the problem? A transient suppressor? Details? Suggestions? Thanks, Bob
ksbszabo@wateng.UUCP (Kevin Szabo) (12/06/84)
The problem with CMOS is that there are many P-N-P-N structures between Vdd and Vss. As most of you know this is a SCR (Silicon Controlled Rectifier) Structure, and is quite sensitive to High dV/dT (transients). I would suggest putting a small capacitor across the line. The impedance of a telephone line is 600 ohms, so the reactance of the capacitor should be quite a bit higher so that it doesn't attenuate the high frequency components. I would try a cap that gave 1K ohm at 5khz, Xc = 1 / ( 2 * pi * C ) ... === 31 * 10 ^ -9 Farad. Which sounds a little high... maybe start with .001 micro farad and then try moving up to to the .031 micro farad cap. Remember that the ring voltage is 90v p-p supermiposed on the 45v dc that is normally on the line. I forget the frequency, but it is below 1000 hz (20 Hz?). Anyway, your cap shouldn't be polorized, and should be good for 200 V. I trust your friend is on an old step-by-step Central Office... I think capacitors on the line would probably confuse a modern CO. With regards to Latch - Up, (plug time) we have some people doing interesting research that will predict latch up paths in VLSI circuitry. It is a difficult problem for CMOS designers since Latch - Up is a very large problem yet one which still has to be check for manually (i.e. look at the I.C. masks and identify the suspect P-N-P-N between Vss and Vdd). A grad student here has modified a circuit extractor to Identify these paths and analyze them for latch-up susceptibility. Very nice. Kevin -- Kevin Szabo watmath!wateng!ksbszabo (U of Waterloo VLSI Group, Waterloo Ont.)