kap@eng.cam.ac.uk (Kevin A.Price) (11/13/90)
Does anyone out there understand (or even have documentation) on the different setups for the following Chips & Technologies chips. I would like to know the following about the 82C206.. XIOR/XIOW Wait States 16 Bit DMA Wait States 8 Bit DMA Wait States EMR Bit CLK Bit And the following about the 82C301... Processor Clock Select Power Fail Warning Ready Timeout Enable AT Bus 32 Bit Cmnd Delay AT Bus 16 Bit Cmnd Delay AT Bus 8 Bit Cmnd Delay AT Bus I/O Cmnd Delay 32 Bit AT Bus Wait States 16 Bit AT Bus Wait States 8 Bit AT Bus Wait States AT Bus Clock Source Also the following about the 82C302... Middle Boot Write Protect Middle Boot ROM Control 16MB I/O Memory Limit Min. Memory Configuration Single Bank/Interleave RAM/ROM Configuration RAM/ROM Control Map RAM at 040000-05FFFFH Map RAM at 060000-07FFFFH Map RAM at 080000-09FFFFH Map RAM at 0A0000-0BFFFFH Map RAM at 0C0000-0DFFFFH Map RAM at 0E0000-0FFFFFH Bank 0/1 DRAM Type Bank 0/1 Starting Address Bank 0/1 RAS Precharge Bank 0/1 Wait States Bank 2/3 DRAM Type Bank 2/3 Starting Address Bank 2/3 RAS Precharge Bank 2/3 Wait States Parity Check First 256K AF32# Control Thanks in advance Kevin Price e-mail kap@eng.cam.ac.uk or kap@rasp.eng.cam.ac.uk or kap@uk.ac.cam.eng