[comp.sys.ibm.pc.misc] High resolution timing

phil@eos.arc.nasa.gov (Phil Stone) (12/12/90)

Excuse me if this is a commonly-discussed topic, but I need a processor-
speed-independent timing utility that gives me millisecond-accurate delay
capability.  Someone is sending me some routines which use Timer 0 on
the 8253 chip; from what I gather, the method is to put the chip into
Mode 2, so that it counts down by ones, allowing its register to be
read directly for the residual count.  The documentation claims that this
has no adverse affects on system Time-of-Day, nor does there seem to be
a "cleanup" routine which sets the timer chip back to its original state
on exit.

Is this indeed a safe method?  If so, why is Mode 3 (counting down by two's
for two loops) even used as the default?

BTW, this utility also accounts for midnight rollover of the counter, so
don't bother warning me about that.  

Thanks for your patience if this is a trivial question, and thanks in
advance for any advice.  Please email if possible; if warranted, I will
post a summary.

		Phil Stone (phil@eos.arc.nasa.gov OR ...!ames!eos!phil)

curci@ds1.scri.fsu.edu (Raymond Curci) (12/15/90)

In article <7675@eos.arc.nasa.gov> phil@eos.arc.nasa.gov (Phil Stone) writes:
>Excuse me if this is a commonly-discussed topic, but I need a processor-
>speed-independent timing utility that gives me millisecond-accurate delay
>capability.  Someone is sending me some routines which use Timer 0 on
>the 8253 chip; from what I gather, the method is to put the chip into
>Mode 2, so that it counts down by ones, allowing its register to be
>read directly for the residual count.  The documentation claims that this
>has no adverse affects on system Time-of-Day, nor does there seem to be
>a "cleanup" routine which sets the timer chip back to its original state
>on exit.
>
>Is this indeed a safe method?  If so, why is Mode 3 (counting down by two's
>for two loops) even used as the default?
>
>BTW, this utility also accounts for midnight rollover of the counter, so
>don't bother warning me about that.  

If you need code to perform timing on all PC/XT/AT/386 systems and need
something finer than the 1/18.2 tick timer, I recommend using the
8253/8254 timer chip  (most PC and XT systems used the 8253; newer
systems tend to use the 8254 which as near as I can tell is register
compatible).  This timer chip has three channels -- 
channel0 - used by the system for a software time-of-day tick counting
   This timer counts to 64K and interrupts the system 18.2 times
   per second.
channel1 - used for DRAM refresh -- don't mess with it
channel2 - used for speaker control (also used in old PC for cassette 
   tape interface)
The 8255 chip has an output bit that controls a latch to disable the
speaker.  Once disabled, you can mess with channel2 without making any
sound.  The output from this timer on the original PC is also wired to
an input pin on the 8255 which could be used to see when the timer
expired when used in a countdown mode, but I recommend you avoid using 
this fact as I have run into clones that do not implement this. 
Instead, I recommend initializing the counter to count down and signal
the chip using OUT commands to latch the counter and IN to read the
current setting.
All systems I have tested feed an input frequency of (4.77/4)Mhz
 -- regardless of  the system clock speed -- so this approach is 
system independant.  I have written some short C language functions
that provide this type of timing service under Microsoft C v6.0 --
let me know if anyone would like a copy.

Ray
--
Raymond Curci                     INTERNET: curci@mailer.scri.fsu.edu
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Florida State University          BITNET:   curci@fsu.bitnet

jrv@sdimax2.mitre.org (VanZandt) (12/18/90)

In article <7675@eos.arc.nasa.gov> phil@eos.arc.nasa.gov (Phil Stone) writes:
>Excuse me if this is a commonly-discussed topic, but I need a processor-
>speed-independent timing utility that gives me millisecond-accurate delay
>capability.  

Thomas Plum and Jim Brodie have code for a microsecond resolution timer
in their book "Efficient C" from Plum Hall.  Note that corrections are
needed for TSRs which have hooked the timer interrupt.

                       - Jim Van Zandt