mmm@cup.portal.com (Mark Robert Thorson) (01/25/91)
I'm trying to figure out the value of paged vs. paged-interleaved memory in PC's with multiple banks. These are both techniques for keeping a DRAM page active in each bank when you have more than one bank of DRAM. In the paged-interleaved system, the banks are interleaved, hence one RAS timeout counter and one set of page hit/miss comparison logic is all that is needed. Essentially, you have the same page being kept active, but it is spread out over all of your banks (usually two or four banks, sometimes eight). You only get a performance penalty when you make an access to another page. In a well-implemented paged system (w/o interleaving) you have separate timeout counters for each banks, so if you have four banks you can have four active pages. These pages are restricted to the address ranges of each bank, e.g. in a system with four 1M banks, you might have one active page available in the range 0 to 1M, a second in the space from 1M to 2M, third in 2M-3M, and the fourth in 3M to 4M. Your program could be hopping around between these four spaces without incurring any extra wait states, unlike the paged-interleaved model which only has one active page (albeit a page 4X larger). Ideally, the paged w/o interleaving system might give you near-zero-wait state performance, if you were using one page to access code space, another page for the stack, and using the other pages to access data. In practice, I think this would be hard to achieve, because it requires your application software to know about your memory architecture. So I would guess that paged w/o interleaving is a loser compared to paged/interleaved. But maybe I'm wrong; Appian (formerly ZyMOS) claims their System 90/SX chipset achieves an average of 0.1 wait state when four DRAM banks are used. They implement paging w/o interleave with four independent sets of page hit/miss logic and RAS timeout counters. Has anybody here studied this question? 0.1 wait state performance sounds pretty good to me, but I see that this sort of memory architecture is vunerable to performance tweaks that ordinary users with their shrink- wrapped software are unable to use. I.e., if your benchmark is delibrately designed to keep separate pages alive in each megabyte the performance would seem artificially high.
phil@brahms.amd.com (Phil Ngai) (01/26/91)
In article <38421@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes: |I'm trying to figure out the value of paged vs. paged-interleaved memory |in PC's with multiple banks. These are both techniques for keeping a |DRAM page active in each bank when you have more than one bank of DRAM. One issue you left out is access time. If you have page mode 100 nS DRAM, your minimum cycle time is about 80 nS or so. (50 nS access time, plus 5 ns rise/fall time, 10 ns setup time, 10 prop time, etc) This is hard to take to 25 MHz. (not impossible, but challenging) If you do page mode and interleaving, then you can reduce your minimum cycle time. -- When someone drinks and drives and hurts someone, the abuser is blamed. When someone drinks and handles a gun and hurts someone, the media calls for a gun ban.