schwalbe@pinocchio.encore.com (Jim Schwalbe) (12/29/90)
I just upgraded my system to a 386SX-20 with AMI BIOS (dated 4/9/90) and the
Chips & Technology chip set. As I was running the XCMOS Setup program and
playing with a few of the parameters, I noticed something strange. Seeing
as how this is a farily common combination, I thought others might have
noticed the same thing. I varied a few things; the Wait States (0/1),
memory interleaving (enabled/disabled) and the shadowing (enabled/disabled).
I also changed the CPU clock speed (8/10/16/20 MHz). Then I ran Norton 5.0
System Information (SI) Benchmark for CPU performance. The first thing I
noticed was the shadowing had no effect on the Norton SI under any of the
above conditions. I confirmed that the shadowing was working by running
Manifest Memory Timings and I could see the speed improve in the shadowed
areas. Norton's benchmard doesn't seem to pick this up. These are the
results I got from varying the other parameters:
(BTW, I am running with 4 Meg of 80 ns 1Mx9 SIMMs in Bank 0 and Bank1)
1 WS 1 WS 0 WS 0 WS
Speed | Int. Disabled Int. Enabled Int. Disabled Int. Enabled
--------+---------------------------------------------------------------
8 MHz | 4.6 3.1 5.8 4.0
--------+---------------------------------------------------------------
10 MHz | 5.8 3.9 7.4 5.0
--------+---------------------------------------------------------------
16 MHz | 9.5 6.3 11.8 7.9
--------+---------------------------------------------------------------
20 MHz | 11.8 7.9 Hangs 10.0
--------+---------------------------------------------------------------
My Observations:
1.) Performance does seem to scale with speed. Good.
2.) With interleaving disabled, adding a wait state to the accesses does
slow things down. Good.
3.) Enabling interleaving seems to slow things down? Why would 0 WS with
interleaving be slower than 1 WS without interleaving? The only thing
I can figure is that with interleaving, each access has one (or more) WS
but they overlap to get an effective 0 WS when actually there is a WS in
each individual access. So where is the advantage of interleaving here?
Has anyone figured this out?
4.) The system won't run at 0 WS without interleaving with 80 ns RAMs? At 20
MHz, 2 bus cycles is 100 ns. Is there that much overhead through the C & T
Chipset? Will 70 ns RAMs get me to 0 WS non-interleaved?
.---------------------------------------------------------------------------.
: Jim Schwalbe .----------------. "Half of what I say is :
: Hardware Research Group .--+-------------. | meaningless; but I say it :
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: schwalbe@encore.com `----------------' - Kahil Gibran :
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