stolk@fwi.uva.nl (Emperor) (04/16/91)
Hi, I am trying to figure out those RAM wait states. I own a 386/33 with a cache. The cache enables the RAM to operate at 0 waitstate for 9x% of the time. But in case of a cache miss, the RAM has to be accessed -> waitstate needed anyway, despite of cache. Well, my CPU runs at 33MHz -> 1 clock cycle takes 30 ns. The RAM I use is 80 ns. So to access RAM, the address has to be on the addressbus for 3 states, then the result can be read. What I think that happens is this: The CPU puts the address on the bus (1 state), then should wait 2 states, and then can read the RAM. (or write for that matter). So my guess is : 2 waitstates for 33MHZ, 80ns RAM. The thing is: my motherboard manual tells me differently: 3 waitstates for read, 1 for write. How can this be? And why are the figures different for read and write? Could someone please help me out on this one? Thanks in advance, PS: Does someone now what 'fast A20 disabled' means? Bram Stolk (stolk@fwi.uva.nl)