osmoviita@cc.helsinki.fi (04/18/91)
In article <1991Apr8.154643.784@saturn.uucp>, martin@saturn.uucp (Martin J. Schedlbauer) writes: > > Many 486 system allow one to disable caching of memory in the upper address > ranges. This is important for memory-mapped I/O cards such as VGA, etc. > How does VGA (SuperVGA) etc. suffer from caching? Kari Osmoviita osmoviita@cc.helsinki.fi
phil@brahms.amd.com (Phil Ngai) (04/19/91)
osmoviita@cc.helsinki.fi writes: >How does VGA (SuperVGA) etc. suffer from caching? If you cache writes, then the cache grabs the write and the VGA card doesn't get it. -- The best way to preserve your RKBA is to vote Libertarian.
osmoviita@cc.helsinki.fi (04/21/91)
In article <1991Apr18.192814.21504@amd.com>, phil@brahms.amd.com (Phil Ngai) writes: > osmoviita@cc.helsinki.fi writes: >>How does VGA (SuperVGA) etc. suffer from caching? > > If you cache writes, then the cache grabs the write and > the VGA card doesn't get it. Have You experienced real problems or is this theoretical thinking? I have not heard before of any such problems, and not seen them myself. Could You explain more in detail. I wouldn't mind not to write same value to same pixel if it is already there. But do You mean that if same places of different pages are written after each other the cache won't let the data through? Or what?? Kari Osmoviita osmoviita@cc.helsinki.fi
phil@brahms.amd.com (Phil Ngai) (04/21/91)
osmoviita@cc.helsinki.fi writes: >Have You experienced real problems or is this theoretical thinking? I have You asked how it (could) suffer. I posted one way. If you don't like it, don't take it. >I wouldn't mind not to write same value to same >pixel if it is already there. Sorry, but caches don't work that way. Caches also work real poorly with paged memory, which the VGA frame buffer is. Just how do you think they fit 256 Kbytes of RAM into the 64 Kbyte segment starting at A000? >But do You mean that if same places of >different pages are written after each other the cache won't let the data >through? Or what?? Could be. There are many different types of caches, your description is one popular way. -- It doesn't have to be perfect to be useful.
glew@pdx007.intel.com (Andy Glew) (04/22/91)
>>>Many 486 system allow one to disable caching of memory in the >>>upper address ranges. This is important for memory-mapped I/O cards >>>such as VGA, etc. >> >>How does VGA (SuperVGA) etc. suffer from caching? > >If you cache writes, then the cache grabs the write and the VGA card >doesn't get it. (1) the i486(tm) on-chip cache is write-through, so this scenario cannot happen within the on-chip cache. It could happen, however, in an i486(tm) system with an off-chip as well as the on-chip cache. (2) In general it is not a good thing to cache I/O memory locations. Many I/O memory locations are "active" - i.e. a read operation may have a side effect, like taking a character off a queue. Caching data so that subsequent reads do not go to the bus means that successive reads will return the same character - not at all what you want. It is possible to imagine caching some aspects of memory mapped I/O. For example, one might put a frame buffer in write through cached memory (but put all the control registers in uncached memory). Then, bitblts in the frame buffer might gain the advantage of caching for reads, but the writethrough would guarantee that all things drawn are seen immediately. Usually, however, the safe and conservative thing to do is not to cache any memory mapped I/O locations. What systems do cache I/O locations? What assumptions do they make (i.e. do they assume write-through? are there control registers read-safe?) How much performance benefit do they get? Please email replies to me, as I do not get to read this newsgroup as often as I should. -- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497 This is a private posting; it does not indicate opinions or positions of Intel Corp.