wolf@mel.cipl.uiowa (07/03/90)
What speed are the ram chips in the standard SE? I am going to buy more memory and I was wanting to know the speed so I can decide on what speed of chips to buy. MJW WOLF@MEL.CIPL.UIOWA>EDU
austing@Apple.COM (Glenn L. Austin) (07/05/90)
wolf@mel.cipl.uiowa writes: >What speed are the ram chips in the standard SE? Depending upon when you received your machine, they could range from 150ns (the slowest allowed on the Mac) to 100ns. However, the only restriction is that all SIMMs within a bank (2/bank on Plus & SE, 4/bank on II-class, & SE/30) are the same speed. -- ----------------------------------------------------------------------------- | Glenn L. Austin | "Turn too soon, run out of room, | | Auto Racing Enthusiast and | Turn too late, much better fate" | | Communications Toolbox Hacker | - Jim Russell Racing School Instructors | | Apple Computer, Inc. | "Drive slower, race faster" - D. Waltrip | | Internet: austing@apple.com |-------------------------------------------| | AppleLink: AUSTIN.GLENN | All opinions stated above are mine -- | | Bellnet: (408) 974-0876 | who else would want them? | -----------------------------------------------------------------------------
rubinoff@linc.cis.upenn.edu (Robert Rubinoff) (07/05/90)
In article <42654@apple.Apple.COM> austing@Apple.COM (Glenn L. Austin) writes: >wolf@mel.cipl.uiowa writes: >[...] However, the only restriction >is that all SIMMs within a bank (2/bank on Plus & SE, 4/bank on II-class, & >SE/30) are the same speed. NO! NO! NO! NO! NO! I'm really getting tired of seeing this wrong information repeated over and over again! If you think about it, you'd realize that this can't possibly be true! The speed rating on a chip is only the guaranteed worst speed the chip will display. A chip rated at 150ns might actually respond within 120ns, or 100ns, or 117.5ns, or any other speed <=150ns. Thus there is no possible way to get SIMMS that are "the same speed". This mistake is presumably a misunderstanding or misremembering of the correct restriction that all SIMMS within a bank must be the same *size*. There is also a restriction on all Macs other than the IIci that if the two banks have different size SIMMS, the larger ones must go in the first bank. (I think the "first" bank is always the one labeled Bank A, but I'm not sure.) I don't mean to criticize Glenn; he's probably just repeating what he was told. But I've seen this misinformation dozens of times, and I'm just getting tired of it. Robert
pscchris@ubvmsd.cc.buffalo.edu (Christopher Holoman) (07/06/90)
In article <26729@netnews.upenn.edu>, rubinoff@linc.cis.upenn.edu (Robert Rubinoff) writes... >In article <42654@apple.Apple.COM> austing@Apple.COM (Glenn L. Austin) writes: >>wolf@mel.cipl.uiowa writes: >>[...] However, the only restriction >>is that all SIMMs within a bank (2/bank on Plus & SE, 4/bank on II-class, & >>SE/30) are the same speed. > >NO! NO! NO! NO! NO! > >I'm really getting tired of seeing this wrong information repeated over and [correction deleted] >This mistake is presumably a misunderstanding or misremembering of the correct >restriction that all SIMMS within a bank must be the same *size*. There is >also a restriction on all Macs other than the IIci that if the two banks have >different size SIMMS, the larger ones must go in the first bank. (I think >the "first" bank is always the one labeled Bank A, but I'm not sure.) Well, I'll add my own correction, or clarification, here. There is a lot of confusion about SEs, which I have recently waded through, caused by what is the "first" bank. If you are upgrading to 2.5 megs, in an older SE, with soldered resistors, the 1 megs go in what I would consider the first bank, since it's labelled SIMM 1 and SIMM 2. BUT, in newer SEs, with the jumper resistor, they must be in the bank labelled SIMM 3 and SIMM 4. I suppose if you ignored the labelling, that bank could be considered "first" since it is closer to the edge of the circuit board. >I don't mean to criticize Glenn; he's probably just repeating what he was told. >But I've seen this misinformation dozens of times, and I'm just getting tired >of it. Ditto. > Robert Chris
russotto@eng.umd.edu (Matthew T. Russotto) (07/06/90)
In article <26729@netnews.upenn.edu> rubinoff@linc.cis.upenn.edu (Robert Rubinoff) writes >If you think about it, you'd realize that this can't possibly be true! The >speed rating on a chip is only the guaranteed worst speed the chip will >display. A chip rated at 150ns might actually respond within 120ns, or 100ns, >or 117.5ns, or any other speed <=150ns. Thus there is no possible way to get >SIMMS that are "the same speed". Why don't you talk to the apple engineer who wrote the tech note on the subject? It may be misinformation, but it comes right out of the tech notes-- #176, written by Cameron Birse... -- Matthew T. Russotto russotto@eng.umd.edu russotto@wam.umd.edu ][, ][+, ///, ///+, //e, //c, IIGS, //c+ --- Any questions? Hey! Bush has NO LIPS!
rubinoff@linc.cis.upenn.edu (Robert Rubinoff) (07/06/90)
In article <1990Jul5.183212.25939@eng.umd.edu> russotto@eng.umd.edu (Matthew T. Russotto) writes: >In article <26729@netnews.upenn.edu> rubinoff@linc.cis.upenn.edu (Robert Rubinoff) writes >>[discussion of why SIMMS don't have to be (can't be) the same speed deleted] >Why don't you talk to the apple engineer who wrote the tech note on the >subject? It may be misinformation, but it comes right out of the tech notes-- >#176, written by Cameron Birse... True, but the tech note only says that the IIci requires the same speed within a row, not the other Macs. And I've heard this alleged requirement long before the IIci came out. I have to admit, I don't understand how this could be required even for the IIci, given that an "80ns" SIMM might really be a "40ns" or "60ns" SIMM; in fact, the individual chips within the SIMM probably all have different speeds. So either the tech note is wrong, or there's something going on I don't understand; either of these is possible, of course. Robert
russotto@eng.umd.edu (Matthew T. Russotto) (07/06/90)
In article <26746@netnews.upenn.edu> rubinoff@linc.cis.upenn.edu (Robert Rubinoff) writes: >In article <1990Jul5.183212.25939@eng.umd.edu> russotto@eng.umd.edu (Matthew T. Russotto) writes: >>In article <26729@netnews.upenn.edu> rubinoff@linc.cis.upenn.edu (Robert Rubinoff) writes >>>[discussion of why SIMMS don't have to be (can't be) the same speed deleted] >>Why don't you talk to the apple engineer who wrote the tech note on the >>subject? It may be misinformation, but it comes right out of the tech notes-- >>#176, written by Cameron Birse... > >True, but the tech note only says that the IIci requires the same speed within >a row, not the other Macs. And I've heard this alleged requirement long before >the IIci came out. Wrong. My copy of TN176, dated April '89 (I have new ones around here somewhere...) has this little note on EVERY diagram, from the Plus through the IIcx. -- Matthew T. Russotto russotto@eng.umd.edu russotto@wam.umd.edu ][, ][+, ///, ///+, //e, //c, IIGS, //c+ --- Any questions? Hey! Bush has NO LIPS!