johnmac@fawlty.towers.oz (John MacLean) (05/30/90)
>You're missing my point! >[ about the extra number of chips on the motherboard ] >when you are laying out the motherboard. As I said, it is the CHIP COUNT and >BOARD AREA that cost so much; the parts themselves can usually be obtained >cheaply in quantity. I do not think I am missing your point - I am not talking about the amount of memory on the board either, but rather the number of chips as you are. Your solution, which is the same as mine, suggests lowering, or at least keeping the chip count the same. It makes no difference whatsoever how you arrange memory (to the number of RAM chips required). 1 magabyte of memory is still 1 megabyte whether it is grouped in chunks of 8 bits or 16 bits. >>IMHO it was a bad move to put more RAM on the motherboard of ROM 03, >Ah, but the ROM 03's Megabyte *is* necessary RAM. Of course it is, but that does not mean it must be on the motherboard, just that it must come as a minimum standard with the system. Anything that comes on the motherboard cannot be replaced without great expense. >Apple did the right thing with the meg in the ROM 03. I admit I would rather >see a movement over to SIMMs, but such a move should accompany a true redesign >along the lines of my //f proposal. Well, they almost did the right thing - the memory is required, but we are stuck with what they have given us. >>This is a 16 bit increment on to one of the two banks. >It's a 24 bit increment. Data accesses may cross bank boundaries. Sorry about that, a small slip, but I am sure that anyone following this got the message. >>[Stuff about extra board complexity etc deleted] >>It is so small that it is dwarfed by current memory management logic that >>deals with shadowing, various banks in the $C000 area and $D000 area, >>alternate zero page etc, etc, etc. >You are assuming they cost nothing; my point is that they are a major cost >factor in actual manufactured motherboards. I agree a new board (for the GS) would be more complex, but the long term benifits would be great. We obviously have different views on just how much more complex; I can live with that. >I contend that a decently designed 8 bit system with page moded DRAMs and >a simple cache system would be more _cost_effective_ then what you are >proposing. Again, I am not arguing with this either. This is probably true. What I am saying is that making a 65816 with a wider data bus would open doors for much faster 65816 based systems in the future. Up to twice as fast as 8 bit data bus systems (with the same caching). >I think a 16 bit wide data bus would be excellent for 2 things: > an accelerator that has its own memory system & SIMM sockets on board > a totally new machine that is not GS compatible. I never once said that this was the way the GS should be improved. To do so would be totally rediculous: for one such a chip does not even exist, and would take at least a year if someone started working on it now. Then we could think about designing the new GS. I was merely presenting what could be done with such a chip if it did exist. If I was to design a new IIGS I would look at currently available technology, what users want, future expandability, and cost. If I was to design a range of new IIGSs and a 16 bit data bus 65816 existed, then I would certainly consider using it in high performance machines. We all know Apple is not going to do this, but I *AM* holding onto hope that they will release a single improved IIGS. Your paper (Apple //f) suggests a fairly sensible way to go, and most of it cannot be argued with (no need to be so paranoid - I am not attacking it). >If this method is really so feasible, then _why_ haven't the big names used it? Take a good look at the 68000 series and the Macs; ever had the system bomb while accessing memory at an odd address; I wonder what the reason for this could be. (HINT: count the address and data lines on early 68000s). Is Motorola or Apple a big name? >Todd Whitesel >toddpw @ tybalt.caltech.edu Regards, John MacLean. -- This net: johnmac@fawlty.towers.oz.au Phone: +61 2 427 2999 That net: uunet!fawlty.towers.oz.au!johnmac Fax: +61 2 427 7072 Snail: Tower Technology, Unit D 31-33 Sirius Rd, Home: +61 2 960 1453 Lane Cove, NSW 2066, Australia.
toddpw@tybalt.caltech.edu (Todd P. Whitesel) (05/31/90)
In article <210@fawlty.towers.oz> johnmac@fawlty.towers.oz (John MacLean) writes: [ a bunch of stuff I largely agree with, except one thing ] putting 1 meg fixed on the motherboard makes a lot of sense, considering that not much else changed. Your argument against it doesn't hold up because the same thing could be said about the built-in RAM on the ROM 01. I agree that socketed chips are far safer and that DIPs let you replace them one at a time, but as memory gets more and more reliable and prices come down ($60 for a 1 meg SIMM these days) there are fewer reasons to use DIPs, especially because SIMMs are sturdy little cards rather than a sets of chips which must be individually installed. The arguments against SIMMs are mostly uninformed paranoia at this point, IMHO. (I speak as one who was slowly convinced over the last year.) >Take a good look at the 68000 series and the Macs; ever had the system bomb >while accessing memory at an odd address; I wonder what the reason for >this could be. (HINT: count the address and data lines on early 68000s). Do your homework. The 68000 series was intended from the start to use a word wide bus; you are supposed to get a bus error if you try to access a word at an odd address. (BYTE accesses work fine at any address.) This was a conscious decision on the part of Motorola to avoid the extra memory circuitry. Given that they were designing the system from scratch, it was a pretty smart thing to do because then nobody would write code that used odd addresses all over the place -- on the 8086 the CPU takes a performance hit because it does two bus accesses for every odd word since you obviously forgot to word align your data structures in the assembler. However, the 68020 & up take a similar performance hit from non-long-aligned long accesses, and do two bus accesses. >Is Motorola or Apple a big name? By 'big names' I meant Motorola and Intel, neither of whom have implemented a scheme with "smart memory" in it (to my knowledge). I figure that they must have considered the idea but decided against it. I still feel that if you are going to give the 65816 a wider data bus then a cache system designed for it will be much more cost-effective than a "smart memory" system. Caches simply aren't as expensive as they used to be. Todd Whitesel toddpw @ tybalt.caltech.edu