jb10320@uxa.cso.uiuc.edu (Desdinova) (09/27/90)
In article <1990Sep26.194057.371@uokmax.ecn.uoknor.edu> you write: >In article <8139.apple.net@pro-angmar> m.tiernan@pro-angmar.UUCP (Michael Tiernan) writes: >>In-Reply-To: message from herwin@pro-novapple.cts.com >> [doubts about new RISC from Apple] >> - Phil Ochs > > Except the 6502 isn't a RISC chip. Why? well: > > 1. RISC machines execute an instruction per cycle. the 6502 doesn't No, but it pipelines- which is why it kicks a '286s butt (at appropriate MHz) > 2. RISC machines have a large number of general purpose registers. the > 6502 doesn't. Uh, actually the 6502 has 256 of them. They're called "Zero Page Addressing" Access to and from zero page is two cycles- same as an A,X, or Y access. So, the 6502 actually is a RISC processor- quite ahead of its time, and able to stand on its own against competition- IF Apple would market it. > I heard rumors that Apple was working on an 88000 based box that would run > mac stuff. But then again, I just HEARD this :) This isn't a rumor. I accept this as fact. Apple bought their Cray to design that system. My interviewer said everything BUT "88000 box to run Mac software" (i.e., he tried to be vague, but I could read what he was trying to hide). Note that the 88000 will work on its own, but will have the capability to run Mac stuff so Mac users are complacent about their machine's death when it comes in two years. > > Collin Douglas > > cbdougla@uokmax.ecn.uoknor.edu > > I wish I would 'hear' something about the GS. Even a rumor is better than > nothing. Oh. Okay. Apple will stop selling the Apple ][. They'll keep supporting it however. They ARE coming out with a //e emulator for the new low-end color mac. They're still deciding what kind of color hardware to put on it "so the // users will feel comfortable" (quoted from a University end student price deal guy, NOT an official Apple Rep, but who works daily with an official Apple Rep). Apple will try to "wean // users to the Macintosh line" (quote from the guy in charge of Apple <somewhere in Europe- see clari.apple....>) by offering this emulator card for a "<$1000 machine" (quote from University rep again). Frankly, I'm pissed that Apple is trying to screw me out of $3000 MORE than I've already invested in my Apple //. Why couldn't they have the sense to produce a low cost GS/Mac combo machine (the famed "golden gate"). It wouldn't take heck of a lot of effort to do something like this. There's been a 68000 card for Apple //s for many years now, I've used it and it works. I believe in the possibility of the Duet card, and think that's the way to go for GS users who absolutely must have a Mac. What I don't understand is why Apple didn't do it first. I truly hope I've spoiled Apple's plan to "Surprise" the // world into buying macinsloshes. I hate marketing people. -- Jawaid Bazyar | Blondes in big black cars look better wearing Senior/Computer Engineering | their dark sunglasses at night. (unk. wierdo) jb10320@uxa.cso.uiuc.edu | The gin, the gin, glows in the Dark! | (B O'Cult) Apple II Forever! Apple II Infinitum! Give me Woz or Give me Amiga!
jm7e+@andrew.cmu.edu (Jeremy G. Mereness) (09/29/90)
> Excerpts from netnews.comp.sys.apple2: 27-Sep-90 6502 *IS* RISC (was Re: > RIS.. Desdinova@uxa.cso.uiuc.e (3297) > > I wish I would 'hear' something about the GS. Even a rumor is better > than > > nothing. > Oh. Okay. Apple will stop selling the Apple ][. They'll keep > supporting > it however. They ARE coming out with a //e emulator for the new low-end > color mac. They're still deciding what kind of color hardware to put on > it > "so the // users will feel comfortable" (quoted from a University end > student price deal guy, NOT an official Apple Rep, but who works daily > with > an official Apple Rep). > Apple will try to "wean // users to the Macintosh line" (quote from the > guy > in charge of Apple <somewhere in Europe- see clari.apple....>) by > offering > this emulator card for a "<$1000 machine" (quote from University rep > again). Sigh, What I thought. I would have wished Apple would allow someone else to step in (some Japanese companies have made offers) but at least I can stop waiting for the //x that will never come. Please note that I, for one, will never be "weaned" as this suggests. No Apple // clone on a card will stand up to the real thing (what with 5.25 drives and things, I'll bet this card costs a bundle!), and I am not interested in buying an overpriced Mac. And I don't believe that the card is an Apple //gs clone either. It probably just emulates a //c. I will continue to program and develop on my //gs and make it as useful as possible. TCP/IP is my present project. I would like to prove to a few people how capable my machine is, and could have been. I encourage everyone else to do the same. 'nuff said on the matter. It's time to do as much possible with what we have. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |Jeremy Mereness | Support | Ye Olde Disclaimer: | |jm7e+@andrew.cmu.edu (internet) | Free | The above represent my| |a700jm7e@cmccvb (Vax... bitnet) | Software| opinions, alone. | |staff/student@Carnegie Mellon U.| | Ya Gotta Love It. | ------------------------------------------------------------------------
stephens@latcs1.oz.au (Philip J Stephens) (10/03/90)
> > 2. RISC machines have a large number of general purpose registers. the > > 6502 doesn't. > > Uh, actually the 6502 has 256 of them. They're called "Zero Page Addressing" > Access to and from zero page is two cycles- same as an A,X, or Y access. Instructions that use zero page addressing are at least 3 cycles in length, where as instructions using register addressing are only 2. Even so, you could legitimately call zero page as a bank of 256 registers, since all indirect modes (except for the jump instructions) use zero page variables to store the address in, and access is still faster than absolute addressing. I don't think the 6502 is pipelined, though, since instructions are executed singly without overlap. If it was, I would have noticed the timing discrepancy in my assembly language programs years ago :-) </\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\></\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\> < Philip J. Stephens >< "Many views yield the truth." > < Hons. student, Computer Science >< "Therefore, be not alone." > < La Trobe University, Melbourne >< - Prime Song of the viggies, from > < AUSTRALIA >< THE ENGIMA SCORE by Sheri S Tepper > <\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/><\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/>
toddpw@tybalt.caltech.edu (Todd P. Whitesel) (10/03/90)
stephens@latcs1.oz.au (Philip J Stephens) writes: >> > 2. RISC machines have a large number of general purpose registers. the > I don't think the 6502 is pipelined, though, since >instructions are executed singly without overlap. If it >was, I would have noticed the timing discrepancy in my assembly >language programs years ago :-) The 6502 _IS_ pipelined, but in ways that are not very dramatic or even obvious unless you look at the CPU's internal operation in detail. Rockwell touted the pipelining in their 6502 user's guide years ago, it is essentially this: When you do a ADC of something, the last cycle of the instruction is when the actual data byte is read in, right? Immediately after that the next opcode is read so the next instruction has started, right? So when did the 6502 add? It added while the next opcode was being read. The accumulator does not actually hold the new value until sometime during the second half (forget exactly where) of the opcode cycle of the next instruction. That's pipelining. It saves you a cycle on every instruction that does an ALU operation. It may not be as spectacular as what's being done on the monster RISCs these days but it is essentially pipelining. Todd Whitesel toddpw @ tybalt.caltech.edu
araftis@polyslo.CalPoly.EDU (Alex Raftis) (10/03/90)
In article <8879@latcs1.oz.au> stephens@latcs1.oz.au (Philip J Stephens) writes: >> > 2. RISC machines have a large number of general purpose registers. the >> > 6502 doesn't. >> >> Uh, actually the 6502 has 256 of them. They're called "Zero Page Addressing" >> Access to and from zero page is two cycles- same as an A,X, or Y access. > > Instructions that use zero page addressing are at least 3 >cycles in length, where as instructions using register >addressing are only 2. Even so, you could legitimately call >zero page as a bank of 256 registers, since all indirect >modes (except for the jump instructions) use zero page >variables to store the address in, and access is still >faster than absolute addressing. > I don't think the 6502 is pipelined, though, since >instructions are executed singly without overlap. If it >was, I would have noticed the timing discrepancy in my assembly >language programs years ago :-) > Your right, a load/store with lda $6/sta $6 would take a 6502 6 cycles. It'd take 4 to do a move d0,d1 on a 68000. So yes, it's slower, but you get 256 byes rather than 8 words to work with. You'd also have to add a cycle to move a full word on a 65816 and a full 12 cycles on a 6502. As for pipelining, the 6502 definitly uses it. Here's an example from "Pro- gramming the 65816" by David Eyes: Step #1: Fetch instruction opcode ADC Step #2: Interpret the opcode to be ADC of a constant Step #3: Fetch the operand, the constant to be added Step #4: Add the constant to the accumulator contents Step #5: Store the result back to the accumulator The pipliningg of the 6502 allows the chip to do steps 2+3 at the same time by incrementing the PC and getting the constant while it interprets the opcode. Then step 4+5 are made to overlap step #1 of the next opcode, thus making the ADC #$xx work in only 2 cycles. True, this isn't true risk which might be able to do it in less time, but it definitly beats out the 68000 which only runs a simple queue. As a point, the 68000 would take 8 cycles to do an ADDI #$xx,D0 (add xx and put in register D0), six more cycles than the 6502. -- -------------------------------------------------- Internet: araftis@polyslo.CalPoly.EDU America Online: xela (Real Life: Alex Raftis)
rhyde@ucrmath.ucr.edu (randy hyde) (10/04/90)
>> I don't think the 6502 is pipelined...
That was one of its claims to fame. The pipelining isn't as deep as modern
day processors, but pipelining was one of the main reasons the 6502 beat out
the 6800 and edged the Z80 in various benchmarks.
*** Randy Hyde O-)