ts@cup.portal.com (Tim W Smith) (08/20/90)
I noticed an interesting situation when evaluating a host adaptor that shall remain nameless. The SCSI chip on this host adaptor can handle synchronous data transfer. The periods that it can handle are a function of a certain register. There are basically something like 8 different values you can choose for this register, and the actual period is a function of this register and the chip clock speed. We tell the peripheral we can do a period of P1. The peripheral comes back and says it can do P2, with P2 > P1. We can't exactly match P2, so we have to use P3, with P3 > P2. Note that if we slowed down the clock speed of the SCSI chip by a factor of P2/P1, we would be able to use the value that gets a period of P1 at the higher clock speed to get a period of P2 at the lower clock speed, allowing us to have a faster data rate! There is nothing strange here, of course, but in these days of cranking up clock speeds, it's interesting to encounter a situation where we could go faster if the board designer had slowed down! Tim Smith ps: of couse, if a slower clock speed had been used, we would have been fine for that particular peripheral, but there would be others that would go faster at the higher speed, so you can't really win...
mjacob@wonky.Eng.Sun.COM (Matt Jacob) (08/29/90)
Yes- I've noticed this phenomenom too. Slower is not necessarily 'slower'. Strictly speaking, the following might be true: + A SYNC scsi host adapter chip (nameless) might make the statement in its manual 'Can receive SYNC data at 5.6mb/s independent of clock speed'. + During SYNC negotiation, you tell the target you can go that fast. It tells you it can only go 4 mb/s. + Due to integer rounding when you program the transmit maximum in the chip, this 4mb/s cooks down to 3.6mb/s. + However, you may still be lucky and the target will still be able to transmit data to you at 5.6mb/s. -matt