[comp.periphs.scsi] SCSI controller chip

phan@iphase.UUCP (Tai Phan PER) (01/18/91)

Hi,

I have a design that use the Fujitsu SCSI controller chip MB87035.

According to the datasheet of the chip, it can run up to 5MB/s SCSI
transfer rate at 10MHz clock.  But there is a note that if the clock
is faster than 8MHz (or 4MB/s transfer rate) there are timings that
the chip may not comply with the SCSI spec.  For example, at 10MHz
clock, the period is 100ns, the SCSI spec for selection phase is
1200ns, the chip spec is 11Tclk - 30 = 11*100 - 30 = 1070ns.  

I spoke to Fujitsu, they said that with the timings in SCSI-I spec,
particular the deskew delay (45ns), assertion period (90ns), negation
period (90ns), data hold time (45ns)... there is no way that one can run
at 5MB/s and fully comply with the spec.???

Does anyone know a SCSI controller chip that runs at 5MB/s and still
fully complies?  This is just the SCSI-I.  Please Email me at 
uunet!iphase!phan

Thank you for you help.

Tai Phan

garyb@SSD.CSD.HARRIS.COM (Gary Barton) (01/22/91)

In article <340@iphase.UUCP> uunet!iphase!phan writes:
...
>
>I spoke to Fujitsu, they said that with the timings in SCSI-I spec,
>particular the deskew delay (45ns), assertion period (90ns), negation
>period (90ns), data hold time (45ns)... there is no way that one can run
>at 5MB/s and fully comply with the spec.???
>

Assumption: Negotiated sync transfer period is not greater than
	    minimum requirements as described in the standard (235 ns).
	    If it is, more waiting is required, because one of the two
	    end points is to slow to keep up with the max.

From the SCSI spec, sync xfers (target to init) must go like this:
	1) Target drives data lines
	2) Target waits deskew delay (45ns) + cable skew delay (10ns)
	3) Target asserts REQ, and holds REQ high for one min
	   assertion period (90ns).  NOTE: Target can release data
	   lines 45ns after asserting REQ.
	4) Target negates REQ, and holds low for one min negation
	   period (90ns)
	5) if offset < negotiated offset
	       goto 1)

Adding these up, we see a minimum period for each transfer is 235 ns
not including any overheads required to actually drive the signals.
This works out to be approximately 4.25 Mbytes/sec, and this is an
absolute limit.  Due to the afforemention overheads, I expect that
anyone transferring above 4 Mbytes/sec is actually shortening these
minimum periods.  For example, the WD33C93 can transfer at 5
Mbytes/sec, but to acheive this data rate, the system designer must
program the chip to use assertion/negation periods of 75 ns instead of
the required 90 ns.  This is clearly documented in the WD manuals.

That said, there will usually not be a problem at the higher rates
unless you are using a long cable and lots of target devices.
However, don't expect much help from your peripheral vendor if you
want to run one of the maximal configurations at 5 Mbytes/sec.

--
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| Gary Barton                    | System Software Development      |
| Lead Engineer			 | Harris Computer Systems Division |
| garyb@hcx1.csd.ssd.harris.com  | 2101 W. Cypress Creek Rd.        |
| gbarton@ssd.harris.com         | Ft. Lauderdale. FL 33309         |
| uunet!hcx1!garyb               | (305) 974-1700                   |
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

wicklund@arrayb.uucp (Tom Wicklund) (01/25/91)

In <2106@travis.csd.harris.com> garyb@SSD.CSD.HARRIS.COM (Gary Barton) writes:

>Assumption: Negotiated sync transfer period is not greater than
>            minimum requirements as described in the standard (235 ns).
>            If it is, more waiting is required, because one of the two
>            end points is to slow to keep up with the max.

>From the SCSI spec, sync xfers (target to init) must go like this:
>        1) Target drives data lines
>        2) Target waits deskew delay (45ns) + cable skew delay (10ns)
>        3) Target asserts REQ, and holds REQ high for one min
>           assertion period (90ns).  NOTE: Target can release data
>           lines 45ns after asserting REQ.
>        4) Target negates REQ, and holds low for one min negation
>           period (90ns)
>        5) if offset < negotiated offset
>               goto 1)


Where do you get 235ns?  I assume this is the sum of 55, 90, and
90 in items 2, 3, and 4 above.  However, #1 and 2 above can
overlap the target negating ACK.

The actual sequence is (note this is DATA OUT phase only):

        1) Target drives data lines
        2) Target waits deskew delay (45ns) + cable skew delay (10ns)
        3) Target waits until REQ negated for one min negation period
           (90ns) or one transfer period after previous assertion
           of REQ (200ns).
        4) Target asserts REQ, and holds REQ high for one min
           assertion period (90ns).  NOTE: Target can release data
           lines 45ns after asserting REQ.
        5) if offset < negotiated offset
               goto 1)

A synchronous transfer will include 55ns overhead at the start of
the transfer while the data lines are initially driven.  After
this the 55ns setup time for data can overlap the 90ns REQ
negation time.


SCSI requires the following timing (DATA IN example):
				  

     |--------90ns----------------|----------- 90ns -----------|
    _                              ____________________________
REQ  |____________________________|                            |_____
                                  |
                                  |
                   |              |
                   |--- 55 ns ----|----- 45 ns ---|
                   |______________________________
DATA --------------<______________________________>------------------


The minimum requirement is that REQ be asserted 90ns and
deasserted 90ns.  Technically this should allow a 180ns transfer
period (I can't find anything in SCSI-1 specifying a minimum
transfer period in a few minutes looking), though 200ns is
traditionally considered the minimum period.

It is true that some chips like the WD33C93 transfer 5MB/s using
an assertion / negation period of less than 90ns.  This is due to
poor chip design, not anything required by the SCSI standard.