tim@sinix.UUCP (Tim Bissell) (04/12/91)
Hello everyone,
I am looking at writing a multitasking I/O script for the NCR 53C710
SCSI processor. In the preliminary Programmer's Guide for the 710 is
a section which describes in very broad terms the design of such a
script. Apparently it was written long before any means of testing
the concepts were available, and as a result several of the key ideas
will not work on the 710 as shown (they might on the 720 ;-).
I have a few ideas of how to get round some of these problems, but I
would be interested to know what approaches other people have taken.
So has anyone out there written such a thing, and are they willing to share
any ideas/approaches etc. with me? Is anyone in the process of doing
such a thing? If so would they like to bounce ideas back and forth?
Please mail me at the address below, or one of the addresses in my
signature.
{..uunet}!mcsun!unido!sinix!tim
Thanks in advance,
Tim
P.S. I am in the process of talking to NCR about this, but I don't think
they will be a lot of help. I may be wrong, but I thought it was
worth checking out the net as well.
--
Tim Bissell | DoD#174 best: tim@athen.sp4n1.siemens.de
Work:+49 89 636 47366 | hmm:ukc!uel!athen!tim
Home:+49 89 775 742 | "Is life worth living? That depends on the liver"
--
Tim Bissell | DoD#174 best: tim@athen.sp4n1.siemens.de
Work:+49 89 636 47366 | hmm:ukc!uel!athen!tim
Home:+49 89 775 742 | "Is life worth living? That depends on the liver"feustel@netcom.COM (David Feustel) (04/13/91)
I worked for NCR on OS/2 drivers for the 700 chip; it was not designed to work well with Intel architectures. I explained in excruciating detail to NCR what they needed to do to fix the design. The 710 was NCR's answer to my suggestions. They didn't really understand what I was trying to tell them. My advice is to get one of the intelligent caching SCSI controllers that supports the WD1003 interface or forget SCSI altogether for another 2 or 3 years. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.com
jesup@cbmvax.commodore.com (Randell Jesup) (04/15/91)
In article <1991Apr13.164615.1117@netcom.COM> feustel@netcom.COM (David Feustel) writes: >I worked for NCR on OS/2 drivers for the 700 chip; it was not designed to work >well with Intel architectures. I explained in excruciating detail to >NCR what they needed to do to fix the design. The 710 was NCR's answer >to my suggestions. They didn't really understand what I was trying to >tell them. Care to elaborate? I've read the programmers docs for the 700 and 710, and they look like really hot chips. Particularily the reduction in # of interrupts to be serviced by the CPU (in a multitasking environment) would seem to be a large win. The 710's indexing registers mean you don't have to essentially use a code-generator to queue up operations. Note: I work in a 680x0 multitasking environment, since from your comments above that's likely to affect your comparison. -- Randell Jesup, Keeper of AmigaDos, Commodore Engineering. {uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.commodore.com BIX: rjesup Disclaimer: Nothing I say is anything other than my personal opinion. Thus spake the Master Ninjei: "To program a million-line operating system is easy, to change a man's temperament is more difficult." (From "The Zen of Programming") ;-)
feustel@netcom.COM (David Feustel) (04/16/91)
I believe that the chips could be made to work really well with the Intel 386/486 architecture, but I gave up trying to explain to the NCR Colorado Springs people what they needed to do after I saw the results of the first go-round. Especially after it became clear that the ideas we were proposing were being incorporated into the chip being built for the 68000 cpu, but not into our chip. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.com
jesup@cbmvax.commodore.com (Randell Jesup) (04/20/91)
In article <1991Apr16.032356.25777@netcom.COM> feustel@netcom.COM (David Feustel) writes: >I believe that the chips could be made to work really well with the >Intel 386/486 architecture, but I gave up trying to explain to the NCR >Colorado Springs people what they needed to do after I saw the results >of the first go-round. Especially after it became clear that the ideas >we were proposing were being incorporated into the chip being built >for the 68000 cpu, but not into our chip. That doesn't make sense. The same chip is used, as I understand it - it has a little-endian/big-endian bit, and controls for bus arbitration for 680x0/x86. You've made a statement - back it up. Note that I may not see the "problems" since I work with 680x0 machines. -- Randell Jesup, Keeper of AmigaDos, Commodore Engineering. {uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.commodore.com BIX: rjesup Disclaimer: Nothing I say is anything other than my personal opinion. Thus spake the Master Ninjei: "To program a million-line operating system is easy, to change a man's temperament is more difficult." (From "The Zen of Programming") ;-)
feustel@netcom.COM (David Feustel) (04/21/91)
Speaking of multi-threaded i/o with the 700 chip, have you successfully implemented it yet? Question: Why is disconnect/reconnect not handled in hardware by any current SCSI chip? -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.com