a186@mindlink.UUCP (Harvey Taylor) (02/14/90)
I posted this a couple of weeks ago, then some burbles developed
in the feed to Mindlink & then the EuroDevCon happened, so please
to excuse reposting bandwidth waste of humble supplicant...
---
I am putting a bubble memory prototype kit (Intel BPK72A)onto a B2000
card, as an educational project. I have never used PALs before, so I've
been puzzling over PALs and the Tech Ref manual, and I have a couple of
questions.
(1) I was a bit surprised to see that the example PIC doesn't use
UDS* or LDS*. How can one get away with this?
(2) I was puzzled by the equations for some of the pins, that
appeared to introduce a race condition. Something like
SIGNALx = [some terms] + /RES*SIGNALx
When I took a look at the PAL internals, I saw that some of those
pins are both input and output. So, the equation above has the effect
of latching the SIGNAL until reset is asserted, right?
(3) I tried to figure out the required Data line equations to see
if I understood what was going on.
Looking at the PAL values required showed this:
Offset BinOffset Value Inverted
00 0000,0000 1100 * 1100
02 0000,0010 0001 * 0001
04 0000,0100 0000 1111
06 0000,0110 0001 1110
10 0001,0000 0000 1111
12 0001,0010 0001 1110
40 0100,0000 0000 * 0000
42 0100,0010 0000 * 0000
* Not inverted
IF(WE'RE OK),/BD12 = /A6*/A5*/A4*/A3*/A2*/A1 + ; Term for 00
/A6*/A5*/A4*/A3*A2*A1 + ; Term for 06
/A6*/A5*A4*/A3*/A2*A1 + ; Term for 12
A6*/A5*/A4*/A3*/A2*/A1 + ; Term for 40
A6*/A5*/A4*/A3*/A2*A1 ; Term for 42
However, the example equations in the book do not show terms for 06/42.
(3-a) So, am I on the right track?
(3-b) Are there some slight differences between the equations given in
Table 3-4 (Page 43, Tech Ref Manual) and the text on page 36, specifically
there is no term for 06.
(3-c) It would seem that the terms for 40 and 42 have been combined by
ignoring an A1 reference, right?
(4) [Not really necessary, I'm just curious] Can somebody explain this 7M
business. Why would the spec say use 7M = C1* XNOR C3*, instead of just
taking 7M from the bus?
(5) I may have a problem with timing. The bubble memory controller is an
older slower device. Total cycle time for read & write is 1000-1200 ns. A
regular 4 cycle read (or write) is going to take ~560ns on the Amiga,
right? So I will need to insert up to 640ns of wait states, or 5 cycles,
right?
I have more puzzlements, but they are unformed as of yet
and this is enough for now.
<-Harvey
"Progress is the mother of problems." -Chesterton
Harvey Taylor Meta Media Productions
uunet!van-bc!rsoft!mindlink!Harvey_Taylor
a186@mindlink.UUCP