sutherla@qtp.ufl.edu (scott sutherland) (02/27/90)
Well, I have asked several questions about memory expansion and the Amiga, specifically w.r.t. the A2091 and A2630. Now I am more informed AND more confused. What I have been told is that, for the A2091, I need 16 256K x 4 CMOS DRAM 120 ns chips for 2 Megs. I can find these in Computer Shopper for ~8 ea. Now, for the A2630, I have been told that I need, get this, 256K x 4 CMOS DRAM 100 ns chips (or faster). NOW I AM REALLY CONFUSED. How can the A2091, which uses 16-bit RAM, and the A2630, which uses 32-bit RAM, use the same type of chips, with the only difference being the SPEED?????????? If this is true, do I use the same number of the faster chips for 2 Megs on the A2630?? The specs on the A2630 state that it comes with 2 Megs of 100 ns RAM. According to the Amiga World review (March 1990), they should have used 80 ns or 70 ns RAM, like the Hurricane and other '030 boards. AW also says that the 2 Megs on the A2630 are soldered in and would be difficult to remove. My question is this. If I leave the 2 Megs of 100 ns RAM in there and decide to add two more Megs of 32-bit RAM, DO I HAVE TO USE 100 ns RAM, OR CAN I USE 70 OR 80 ns RAM TO IMPROVE PERFORMANCE???? What will be the effect, if any, (especially adverse effects) of having 2 different speeds of RAM on the board? Would I be better off removing the original 2 Megs and using the same chips for all 4 Megs? A couple of extra questions. I have been told that I MUST use CMOS chips and not NMOS chips. None of the places in the Computer Shopper specify whether the chips they list are CMOS or NMOS. How do I differentiate? And finally, Dave Haynie told me that the chips for the A2630 were NOT only 256K x 4 CMOS DRAM 100 ns chips, BUT that they must be in the ZIP package. What in the world is a ZIP package??? Again, none of the advertisers in CS mention anything about ZIP!! They mentions SIMMS, but NO ZIPS. Why do I need ZIP? How do I determine if a chip advertised in CS is ZIP or not??? AS YOU CAN SEE, I AM TOTALLY CONFUSED. ANY HELP IN "STRAIGHTENING ME OUT" WOULD BE APPRECIATED. Thanks, Scott Sutherland sutherla@qtp.ufl.edu
hue@netcom.UUCP (Jonathan Hue) (02/28/90)
In article <928@orange9.qtp.ufl.edu> sutherla@qtp.ufl.edu (scott sutherland) writes: > How can the A2091, which uses 16-bit RAM, and the A2630, which >uses 32-bit RAM, use the same type of chips, with the only difference >being the SPEED?????????? If this is true, do I use the same number >of the faster chips for 2 Megs on the A2630?? The DRAM is 256Kx4 bits, not 16 or 32. Instead of needing 4 chips to provide a 16-bit wide path to memory, you need 8 chips for a 32-bit wide path. 2MB of either is the same number of chips, but the A2630 takes ZIPs and the 2091 takes DIPs > The specs on the A2630 state that it comes with 2 Megs of >100 ns RAM. According to the Amiga World review (March 1990), they >should have used 80 ns or 70 ns RAM, like the Hurricane and other >'030 boards. AW also says that the 2 Megs on the A2630 are soldered >in and would be difficult to remove. My question is this. If I leave >the 2 Megs of 100 ns RAM in there and decide to add two more Megs of >32-bit RAM, DO I HAVE TO USE 100 ns RAM, OR CAN I USE 70 OR 80 ns RAM >TO IMPROVE PERFORMANCE???? What will be the effect, if any, (especially >adverse effects) of having 2 different speeds of RAM on the board? Would >I be better off removing the original 2 Megs and using the same chips for >all 4 Megs? How kind of the writers at AW to share their infinite wisdom with us. 80ns DRAM is going to be close to the edge of being able to drop a wait state (Dave, help). I'm pretty sure 70ns is fast enough to drop a wait state, but I haven't seen 70ns access time DRAM advertised in any of the local microcomputer rags. When performing an asynchronous bus transfer, the '030 waits for a comple signals called /DSACK0 and /DSACK1 to tell it when data is valid and it can grab it off the bus. DRAMs don't have pins that generate these signals, you either roll your own DRAM controller out of PLDs or buy one off the shelf to generate these signals. The system designer decides something like: "Hey, 100ns or faster DRAM is available cheap, so I'll have my PALs generate /DSACK[01] XX ns after /DS and tell the user to use 100ns or faster DRAM to populate this thing." So if you put in 70ns DRAM, the CPU still waits until it sees /DSACK[01] until it grabs the data. There isn't a way for it to know how fast the memory is. Now, I may be dreaming, but I swear I've seen the data sheet for a *programmable* Samsung DRAM controller which could do all sorts of fancy stuff, like generate /DTACK faster of slower for different chunks of memory (address ranges), generate nibble and page mode cycles, etc. If I wasn't dreaming, this thing could be programmed to generate /DTACK faster if you had a chunk of faster memory. >What in the world is a ZIP package??? Again, none of the advertisers in CS >mention anything about ZIP!! They mentions SIMMS, but NO ZIPS. Why do I need >ZIP? How do I determine if a chip advertised in CS is ZIP or not??? ZIP is zigzag. Good luck finding these cheap, let us all know if you find a source. -Jonathan
stevem@sauron.Columbia.NCR.COM (Steve McClure) (02/28/90)
In article <928@orange9.qtp.ufl.edu> sutherla@qtp.ufl.edu (scott sutherland) writes: > > > Well, I have asked several questions about memory expansion and >the Amiga, specifically w.r.t. the A2091 and A2630. Now I am more >informed AND more confused. What I have been told is that, for the >A2091, I need 16 256K x 4 CMOS DRAM 120 ns chips for 2 Megs. I can find >these in Computer Shopper for ~8 ea. Now, for the A2630, I have been >told that I need, get this, 256K x 4 CMOS DRAM 100 ns chips (or faster). >NOW I AM REALLY CONFUSED. > The key here is that memory is memory. 8-bit, 16-bit, 32-bit all refer to the number of bits that can be accessed in one read, in other words in parallel. The chips you need are 256Kx4, x4 means 4 bits in parallel. Therefore you need 4 chips to have memory that is accessable 16 bits at a time. This means you should be able to populate the board in 256K/2*4 increments. ^^^^^^ it takes two chips to make 8 bits or a byte. There is some organization to the chips. The most popular being 256Kx4 and 1Mx1 in 1 megabit chips. The design of the board determines how many bits can be accessed in parallel. > A couple of extra questions. I have been told that I MUST use CMOS >chips and not NMOS chips. None of the places in the Computer Shopper >specify whether the chips they list are CMOS or NMOS. How do I differentiate? >And finally, Dave Haynie told me that the chips for the A2630 were NOT only >256K x 4 CMOS DRAM 100 ns chips, BUT that they must be in the ZIP package. > >What in the world is a ZIP package??? Again, none of the advertisers in CS >mention anything about ZIP!! They mentions SIMMS, but NO ZIPS. Why do I need >ZIP? How do I determine if a chip advertised in CS is ZIP or not??? > Chips come in different packages, or physical designs: Dual Inline Package - DIP's pins are in two parallel rows. ....... ....... Zig-Zag Inline Package - ZIP's pins are in one row, slightly offset. . . . . . . . . A host of others. You usually have to ask about package styles and chip types. Typically, the parts you see advertized in CS are CMOS DIP's for this chip type. Steve ----- Steve.McClure@Columbia.NCR.COM The above are my opinions, which NCR doesn't really care about anyway! CAUSER's Amiga BBS! | 803-796-3127 | 8pm-8am 8n1 | 300/1200/2400
swarren@convex.com (Steve Warren) (03/01/90)
In article <928@orange9.qtp.ufl.edu> sutherla@qtp.ufl.edu (scott sutherland) writes: [...] > How can the A2091, which uses 16-bit RAM, and the A2630, which >uses 32-bit RAM, use the same type of chips, with the only difference >being the SPEED?????????? If this is true, do I use the same number >of the faster chips for 2 Megs on the A2630?? The memory chips are 4 bits wide. When a single location on one chip is addressed, 4 bits of data are output. Four of these chips used in parallel will provide a 16-bit data bus in the case of the 2091. The 2091 cannot be expanded 4 chips at a time, but if the control circuits (and the autoconfig standard) supported it, your four chips would provide 256K X 4 bits X 4 chips = 4 Mbits/(8 bits/byte) = 1/2 Mbyte. So using 16 chips in four blocks of 512 K would give you 2 Mbytes. On the 2630 you need 8 chips in parallel to get the 32 bit data bus. This gives a 1 Mbyte block of 32-bit ram. 16 chips will provide 2 Mbytes. > The specs on the A2630 state that it comes with 2 Megs of >100 ns RAM. According to the Amiga World review (March 1990), they >should have used 80 ns or 70 ns RAM, like the Hurricane and other >'030 boards... The timing of the memory system is not determined by the access times of the memory chips. The timing is determined by the *controller* circuitry which drives the drams. However, if the controller requests data from a chip and the chip does not provide the data in time then the board will essentially output garbage instead of data. In other words, if the chips are too slow, everyone will know it in no uncertain terms. Also, watch out for Amiga World. They are not an authority on everything they talk about (OK, sometimes they are right; I prefer to remember all the times they didn't know what they were talking about ;^). > ...AW also says that the 2 Megs on the A2630 are soldered >in and would be difficult to remove. My question is this. If I leave >the 2 Megs of 100 ns RAM in there and decide to add two more Megs of >32-bit RAM, DO I HAVE TO USE 100 ns RAM, OR CAN I USE 70 OR 80 ns RAM >TO IMPROVE PERFORMANCE???? What will be the effect, if any, (especially >adverse effects) of having 2 different speeds of RAM on the board? Would >I be better off removing the original 2 Megs and using the same chips for >all 4 Megs? As I said, the timing of the system is determined by the controller. Once the controller timing is determined then the drams must be at least X nsec access time drams, because the controller assumes, X nsec after the request is made, that the data is available and is valid. Since dram chips do not come with any outputs that say "the data is now a valid output" the controller simply waits X nsecs and sends whatever is on the output pins of that chip out to the rest of the world. If the data happens to be garbage because the chip is too slow then the controller is perfectly happy to send out garbage (assuming no parity, a safe assumption on the Amiga). What this means is that if the memory controller on the 2630 is designed to expect data 100 ns after a request to the chip, then that is how long it is going to wait. If you replace 100 ns chips with 80 ns chips then the data will be available 20 nsec before the controller needs it. In other words, you gain only increased margin, not performance. [...] >What in the world is a ZIP package??? Again, none of the advertisers in CS >mention anything about ZIP!! They mentions SIMMS, but NO ZIPS. Why do I need >ZIP? How do I determine if a chip advertised in CS is ZIP or not??? I don't know the package codes, but I imagine if you call them you might find someone with zip packages. From what I understand a zip package is a zig-zag in-line package. That is, the chip stands on its side with the leads coming out of the side, but the leads are staggered in a zig-zag pattern. The advantage is that you achieve much of the space-saving potential of a simm, without the added expense. The only trouble is that these packages are much harder to find than dip packages. I don't know why the chips are soldered in, unless the extra capacitance of a socket would be detrimental to the system. Since zips have leads they should be socketable. Probably it was cheaper and presented less quality concerns, since socketed parts have been known to "walk" their way out. > AS YOU CAN SEE, I AM TOTALLY CONFUSED. ANY HELP IN "STRAIGHTENING >ME OUT" WOULD BE APPRECIATED. > >Thanks, > >Scott Sutherland >sutherla@qtp.ufl.edu Hope this helped. -- --Steve ------------------------------------------------------------------------- {uunet,sun}!convex!swarren; swarren@convex.COM
daveh@cbmvax.commodore.com (Dave Haynie) (03/01/90)
In article <928@orange9.qtp.ufl.edu> sutherla@qtp.ufl.edu (scott sutherland) writes: > How can the A2091, which uses 16-bit RAM, and the A2630, which >uses 32-bit RAM, use the same type of chips, with the only difference >being the SPEED?????????? The parts are both 256K x 4 bits. For the 2091, there are 4 chips in a bank -> 4 x 4 = 16. For the 2630, there are 8 chips in a bank -> 4 x 8 = 32. >If this is true, do I use the same number of the faster chips for 2 Megs >on the A2630?? You need 16 chips for 2 megs on the A2630. These are in ZIP packages, vs. the DIP packages used on the A2091. > The specs on the A2630 state that it comes with 2 Megs of >100 ns RAM. According to the Amiga World review (March 1990), they >should have used 80 ns or 70 ns RAM, like the Hurricane and other >'030 boards. AmigaWorld, like many such magazines, tries but doesn't really understand the issues. Putting 80ns DRAM in the A2630 isn't going to help at 25MHz. The timing isn't a continuous thing, it's quantized on 40ns boundaries. You'd undoubtedly loose a wait state going to 70ns parts, but 70ns parts are much more expensive than 80ns or 100ns, currently. >My question is this. If I leave the 2 Megs of 100 ns RAM in there and >decide to add two more Megs of 32-bit RAM, DO I HAVE TO USE 100 ns RAM, OR >CAN I USE 70 OR 80 ns RAM TO IMPROVE PERFORMANCE???? What will be the >effect, if any, (especially adverse effects) of having 2 different speeds of >RAM on the board? Would I be better off removing the original 2 Megs and >using the same chips for all 4 Megs? You could drop in 80ns or 70ns parts and the board will work, but it's not going to run any faster, even if you replace the 100ns parts. DRAM don't set the speed of a system, just the potential. The memory control logic is what desides how fast the DRAM will be run. There's nothing more you can do with 80ns at 25MHz that I'm not already doing with the 100ns parts, though I suppose if all parts were changed to 70ns, the system could easily be re-tuned to run faster. Easily, meaning via a changed PAL; this isn't something the average person could do in a couple of minutes. > A couple of extra questions. I have been told that I MUST use CMOS >chips and not NMOS chips. None of the places in the Computer Shopper >specify whether the chips they list are CMOS or NMOS. How do I differentiate? It doesn't matter for the A2630, but in some systems it may. Over the life of the 256k x 4 parts, most vendors switched from the NMOS processes used in the older 256k x 1 or 64k x 4 parts to CMOS. As a result, most of the CMOS parts are a bit faster here or there, though there's no way to tell for sure other than by checking the data sheet. Based on Commodore's habit of buying any DRAM they can get in the Far East, plus the time at with the A2630 was designed (finished it a year ago, right in the midst of the DRAM price crunch), the A2630 can use any 100ns NMOS part. You have to realize that while the speed rating of a DRAM is how you buy them, that's only one of ten or more very critical timing parameters associated with the particular chip. >And finally, Dave Haynie told me that the chips for the A2630 were NOT only >256K x 4 CMOS DRAM 100 ns chips, BUT that they must be in the ZIP package. The ZIP package is the physical parameter. The board is set up for this, the DIP parts such as those used on the A2091 simply won't fit. >What in the world is a ZIP package??? Start with a normal IC, if you know what these look like. Most DRAMs and TTL are in DIP packages; the package is relatively flat, and there are rows of pins going down both sides. Imagine you can modify this package. Take one row of pins and bend it straight out, away from the body of the part. Now, take the other row of pins, bend them out, and then rotate them around to the same side as your first row. Move them slightly down, so instead of being directly in-line with the first set, they're in sort of a zig-zag arrangement. What you have now is essentially a ZIP package. They're designed for higher density applications; you can fit two ZIPs in the space of one DIP, sometimes even more depending on the width of the DIP. In any case, it's a package. There are DIPs, ZIPs, and surface mount packages for most DRAM. Some companies take a mess of surface mount packages, mount them on a small circuit board according to an industry standard, and produce a module called a SIMM. That's pretty much the physical packaging story. >Scott Sutherland -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
bscott@pikes.Colorado.EDU (Ben M Scott) (03/01/90)
In article <8068@netcom.UUCP> hue@netcom.UUCP (Jonathan Hue) writes: >>What in the world is a ZIP package??? Again, none of the advertisers in CS > >ZIP is zigzag. Good luck finding these cheap, let us all know if you find >a source. The Kruger Company that advertises in Amazing showed 120ns 256x4 ZIP chips for about $3.60 each. They sell used but tested chips that have a 30 day guarantee. I've bought about 16 CPU chips so far and they seem to work; Krueger has fast service, and once you get past the operator/receptionist you're liable to find some fairly nice people; I suggest you ask for Myron Lieberman as mentioned in the ad; he has several Amigas of his own. I am not affiliated with them, only a satisfied customer. If you're not worried about using used chips (they are guaranteed) this is a great place to get incredible prices. An example: 8 Mhz 68010, $1 each. 25 Mhz 68030: $85. They have a minimum order of $50, though; I bought a bunch of '010 chips to fill out my order and have sold most of them for $3 to $5 each; they run great in any Amiga. . <<<<Infinite K>>>>
jma@beach.cis.ufl.edu (John 'Vlad' Adams) (03/01/90)
In article <100326@convex.convex.com> swarren@convex.com (Steve Warren) writes: >The 2091 cannot be expanded 4 chips at a time, but if the control circuits >(and the autoconfig standard) supported it, your four chips would >provide 256K X 4 bits X 4 chips = 4 Mbits/(8 bits/byte) = 1/2 Mbyte. >So using 16 chips in four blocks of 512 K would give you 2 Mbytes. The 2091 certainly CAN be expanded four chips at a time. You can install 512k, 1 meg or two megs. The only increment you cannot do is 1.5 megs. Tomorrow I am ordering 512k. In a month I'll order either another 512k, or if I have the cash, the last 1.5 megs. -- John M. Adams --*-- Professional Student on the six-year plan! /// Internet: jma@beach.cis.ufl.edu -or- vladimir@maple.circa.ufl.edu /// "Houston, we have a negative on that orbit trajectory." Calvin & Hobbs \\X//
daveh@cbmvax.commodore.com (Dave Haynie) (03/02/90)
In article <100326@convex.convex.com> swarren@convex.com (Steve Warren) writes: >I don't know why the chips are soldered in, unless the extra capacitance >of a socket would be detrimental to the system. Since zips have leads >they should be socketable. Probably it was cheaper and presented less >quality concerns, since socketed parts have been known to "walk" their >way out. Part of the reason is, from a reliability point of view, it's always better to solder in something that you don't normally have a need of replacing. So memories and TTL get soldered in, PALs, Amiga chips, and 8520s get socketed. The other reason is that, until quite recently, we didn't have a good socket for the ZIP parts. DIPs work pretty well with all kinds of standard IC sockets. But because of the design, ZIP leads are quite bendable. If you put a ZIP many of the standard DIP socket designs (once you maul them into a zig-zag pattern), you'll find on any given insertion, about 1/2 of the ZIP's pins will bend up instead of going into the socket. Special ZIP sockets don't have this problem, but they also aren't common. >--Steve -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough