finkel@TAURUS.BITNET (06/28/90)
As I promised, here is a summary of all the replies I got. I got 4 replies, which were very helpful! The answers came from: From: grr@cbmvax.commodore.com (George Robbins) From: daveh@cbmvax.commodore.com (Dave Haynie) From: mjulku@ujocs.joensuu.fi (Mikko Julku) From: mpirbn!p554mve@relay.EU.net (Michael van Elst) thanks again for all of you! George, Dave and Michael basically said that if I use an EPROM which is fast enough, I don't have to worry about ~DTACK since it's handled by the GARY chip. Mikko Julko suggested me a circuit for generaing ~DTACK with the required number of wait states, which , in my opinion, is good for a generic 68000 system ( or for an external Zorro II device ), but not for an internal piggyback board, since I don't know any way to DISABLE GARY from generating a Zero wait states ~DTACK pulse. I completed the design, and now I'm waiting to get back the PCB and test it. Below is my original letter, followed by the individual responses, which were slightly edited, mostly to remove large quotes of my letter which appeared again and again in more than one letter. Udi ------------------------------------------------------------------ Hello everyone! I'm doing my 1st 68000 bus design, and I have a question I ran into while designing the circuit. I'm building a ROM expansion card for the Amiga 500. It will plug into the 68000 socket (for a few reasons this is not the place to discuss... YES, there ARE reasons why we DIDN'T do an external AutoConfig design). I want to map the ROMs at $F0XXXX ( 64K Bytes , 2 x 27256 EPROMs ). Basically, this is the design I came up with: One EPROM's D0-D7 goes to the 68000's D0-D7. The other EPROM's D0-D7 goes to the 68000's D8-D15. The 68000's A1-14 goes to both EPROM's A0-A14. The 68000's A16-A23 are connected to 74HCT688 ( 8 bit comparator ). The other 8 bit input of the 74HCT688 is connected to a fixed $f0 value. The 688's ~G (enable) is connected to the 68000's ~AS. The 688's output is connected to both EPROM's ~CS. One EPROM's ~OE is connected to the 68000's ~UDS. The other EPROM's ~OE is connected to the 68000's ~LDS. My question is, what should I do with ~DTACK (from the 68000) ? I understand that every asynchronous memory access done by the 68000 must be terminated by asserting ~DTACK. I know this is done automatically ( by the GARY chip? ) for the Kickstart ROM located at $FC0000. Is ~DTACK generated for any memory reference at $F00000 as well? This is very important to me, and our news system is NOT reliable. In fact, I'm posting this letter using the comp.sys.amiga mail alias at Berkeley, so PLEASE answer by mail, or else I might miss the answer. I will summarize if necessary. thanks, Udi ------------------------------------------------------------------ From: grr@cbmvax.commodore.com (George Robbins) Subject: Re: 68000 bus design question In article <9006202113.AA16069@virgo> <finkel%math.tau.ac.il@CUNYVM.CUNY.EDU> writes: [ letter quote removed by me -udi ] Look carefully at the EPROM timing. For relatively slow EPROM's you get the best timing by grounding chip enable and driving output enable based on something like address_match & _AS & _?DS. You don't really need separate byte output enables, but you can implement either or both with something like a 74LS139 added to your stuff. You can always get fast enough ROM so you don't have to worry about it. > My question is, what should I do with ~DTACK (from the 68000) ? If you don't mess with it, the Gary chip will generate _DTACK for the F0 range. If your timing doesn't require wait states, you're done... ------------------------------------------------------------------- From: mjulku@ujocs.joensuu.fi (Mikko Julku) It says like about this: connect both 688's ~G signals to 74LS174's enable through inverting circuitry (74LS04). Connect CLK to 174's clk. Make d-flip-flops as chain. Invert the resulting signal via 74LS05 with pull-up resistor. 688 ~G ----Do-- 7.159 Mhz clk +----~ EN 174 clk ---+ 688 ~G-----Do-- -------- --------- -------- -------- 1 1 1 1 1 1 1 1 + D Q +---U---+ D Q+--U---+D Q+--U---+D Q+ 1 1 1 1 1 1 1 1 +-> ~Q+ +---> ~Q+ +---> ~Q+ +--> ~Q+ 1 --------- 1 --------- 1 -------- 1 -------- 1 1 1 1 +---------------------------------------------------------- CLK The resulting signal can be taken from U marked spots. (1st U 1 wait, 2nd U 2 wait states ...) . This is all by heart, think yourself also. >I understand that every asynchronous memory access done by the 68000 >must be terminated by asserting ~DTACK. I know this is done automatically >( by the GARY chip? ) for the Kickstart ROM located at $FC0000. Is ~DTACK >generated for any memory reference at $F00000 as well? I think it is, because $F00000 is alternative ROM area at A1000. Interesting point is that boot ROM looks for $1111 and JMP's op code in hex from that address. If these 2 words are found, execution moves to that area with return address in register A5. -------------------------------------------------------------------------- From: daveh@cbmvax.commodore.com (Dave Haynie) In article <9006202113.AA16069@virgo> you write: >Hello everyone! >I want to map the ROMs at $F0XXXX ( 64K Bytes , 2 x 27256 EPROMs ). Basically, >this is the design I came up with: Playing with the old "cartridge" feature, eh. >I understand that every asynchronous memory access done by the 68000 >must be terminated by asserting ~DTACK. I know this is done automatically >( by the GARY chip? ) for the Kickstart ROM located at $FC0000. Is ~DTACK >generated for any memory reference at $F00000 as well? DTACK is generated by Gary for every cycle. Really, the only decisions Gary makes are (a) do I need to pay attention to custom chip activity and (b) is an expansion device driving XRDY or OVR*. If the answer is no to both questions, Gary will generate a 0 wait state DTACK for that memory location. So for your ROM board, you should just be able to leave DTACK alone and expect it to work fine. >Udi Finkelstein | Bitnet: finkel@taurus.bitnet or finkel@math.tau.ac.il Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "I have been given the freedom to do as I see fit" -REM ---------------------------------------------------------------------------- From: mpirbn!p554mve@relay.EU.net (Michael van Elst) Subject: Re: 68000 bus design question In article <9006202113.AA16069@virgo> you write: >I'm building a ROM expansion card for the Amiga 500. It will plug into >the 68000 socket (for a few reasons this is not the place to discuss... YES, >there ARE reasons why we DIDN'T do an external AutoConfig design). > >My question is, what should I do with ~DTACK (from the 68000) ? Hello, DTACK is asserted by GARY for ALL cycles except for the 2 Megabyte space from $a00000 to $bfffff where synchronous cycles are used for the CIA devices. You can simply live DTACK alone. In the A500, the address space of $e00000 to $e7ffff is occupied by a mirror of the system roms but $f00000 to $f7ffff is quite ok. But Future revisions of Gary may use other mappings. Hope that helps. -- Michael van Elst UUCP: universe!local-cluster!milky-way!sol!earth!uunet!unido!mpirbn!p554mve Internet: p554mve@mpirbn.mpifr-bonn.mpg.de "A potential Snark may lurk in every tree."