[comp.sys.amiga.hardware] DAVE HAYNIE

neumann@uniol.UUCP (Frank Neumann) (07/25/90)

Hi guys,

here is couple of questions from a friend of mine. If you don't understand
them (I'm no hardware freak, so I can't help), feel free to mail me
and I will ask him. Here it goes:

1) How can you synchronize the states of the processor clock s0 - s7
   to a stable clock system on the Zorro II slot ?
   Is it possible to identify one of these states to make a synchronization
   of bus cycles on the Zorro II slot (only in the $200000-$9fffff range) ?

2) Does the system assert for its own a wait state to the Zorro II bus,
   or is every cycle closed to another ?

3) Is there a simple way to make a DRAM operation starting at the rising
   edge on s4 and ending at the rising edge of s0 ?
   Is it also possible to make a refresh cycle in a cycle starting with
   the rising edge on s0 and the falling edge on s3 ?

4) Which clock is the best to make a refresh clock with 64 KHz ?
   (I want to divide up the E-clock on pin 50)

5) How do I handle the 32 address and data lines on a Zorro III slot ?

6) Is it a good idea having several autoconfig's ON ONE BOARD ?
   (bit 4 on the autoconfig-address $00/$02 being set on the first config
   and the last (the second) being returned to the system ?

Well, that's it. Quite hard things I suppose, 'cause I didn't understand
a single of these. As I said, if there are questions, mail me, and I will
forward the questions to him... but do so quickly, as I will not be
at my terminal for a couple of weeks after Friday (time for vacations! :))

ANY help appreciated, and thanks in advance,

Frank 'F.N.II(tm)'
-- 
+ Frank Neumann, Hauptstr. 107, 2900 Oldenburg, FRG   The Amiga is it. +
+ neumann@uniol.uucp  ZER:neumann@uniol.zer  InHouse: amigo@faramir    +

daveh@cbmvax.commodore.com (Dave Haynie) (07/26/90)

In article <3155@uniol.UUCP> neumann@uniol.UUCP (Frank Neumann) writes:
>Hi guys,

>1) How can you synchronize the states of the processor clock s0 - s7
>   to a stable clock system on the Zorro II slot ?
>   Is it possible to identify one of these states to make a synchronization
>   of bus cycles on the Zorro II slot (only in the $200000-$9fffff range) ?

If you're really interested in identifying a particular state, try this.
Use the falling edge of the CDAC clock to sample the AS* signal.  When you
see this sampled AS* change from 1 to 0, you are in the middle of S3.  You
can't clock AS* safely during S2, since by definition, it can change 
anywhere within S2.

>2) Does the system assert for its own a wait state to the Zorro II bus,
>   or is every cycle closed to another ?

Every bus cycle is 0 wait state, s0-s7, 4 7MHz clocks, however you would like
to label it.  Asynchronous wait states can be added by bringing the XRDY
line low.  The cycle can be completely controller, 68000-style, by driving
OVR* low and then directly driving the DTACK* signal yourself.

>3) Is there a simple way to make a DRAM operation starting at the rising
>   edge on s4 and ending at the rising edge of s0 ?
>   Is it also possible to make a refresh cycle in a cycle starting with
>   the rising edge on s0 and the falling edge on s3 ?

There are certainly boards which work something like this.  I don't recommend 
running a refresh every cycle, since you're going to EAT power.  For example,
Commodore A2052, probably the first 2 meg board for the 2000 every designed,
refreshes every cycle, and draws 3 Amps because of it.  

>4) Which clock is the best to make a refresh clock with 64 KHz ?
>   (I want to divide up the E-clock on pin 50)

Actually counting refresh is the right way to go.  I did a Zorro III example
design for the Atlanta DevCon which builds a refresh counter using a 16R8
PAL, using the 7MHz clock.  Certainly E could be used as well, and you would
save yourself a state or two in the counter.

>5) How do I handle the 32 address and data lines on a Zorro III slot ?

Basically, you latch the addresses on the falling edge of FCS*, and make sure
you never drive data onto the bus before DOE is asserted.  All Zorro III
cards are 32 bits wide; the number of address lines you need depends on your
design.  I seriously recommend getting the notes from Atlanta's DevCon if
you're planning to do any Zorro III design.  These contain both the Zorro III
specs and an example DRAM board.  CATS/ESCO should eventually have these 
notes bound and printed for sale.

>6) Is it a good idea having several autoconfig's ON ONE BOARD ?
>   (bit 4 on the autoconfig-address $00/$02 being set on the first config
>   and the last (the second) being returned to the system ?

Well, it's no problem.  Though most designs don't have a need for multiple
AUTOCONFIG units, there's no problem building a card that does.  You will,
in general, need a separate address latch and comparator for each unit,
though in some cases the AUTOCONFIG ROM may be shareable between two units,
since it can adjust to the logical unit that's currently being configured.
Don't assert CFGOUT* until everything's configured.

>Well, that's it. Quite hard things I suppose, 'cause I didn't understand
>a single of these. 

None of these questions are that hard, but some have full answers that are
way beyond the scope of what can be answered in a newsgroup.

>+ Frank Neumann, Hauptstr. 107, 2900 Oldenburg, FRG   The Amiga is it. +
>+ neumann@uniol.uucp  ZER:neumann@uniol.zer  InHouse: amigo@faramir    +


-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
           The Dave Haynie branch of the New Zealand Fan Club

amhartma@silver.ucs.indiana.edu (Andy Hartman - AmigaMan) (07/26/90)

Summary: Why didn't I think of that?!?!

References: <3155@uniol.UUCP> <13429@cbmvax.commodore.com>
Sender: amhartma@silver.ucs.indiana.edu
Organization: Indiana University, Bloomington IN.
Keywords: Zorro, clock, synchronizing

---------------------------------------------------
[said as the guys in white coats take me away...]
---------------------------------------------------

Huh? Would you mind repeating that...

B-duh, b-duh, b-duh, that's all folks!
:-)

AMH

* Andy Hartman       | I'd deny half of this crap anyway!| "Somedays, you just
* Indiana University |-----------------------------------|  can't get rid of a
*    //	 Amiga Man   |   amhartma@silver.ucs.indiana.edu |  bomb!" 
*  \X/	 At Large!   |   AMHARTMA@rose.ucs.indiana.edu   | - Batman (original)