lkoop@pnet01.cts.com (Lamonte Koop) (10/15/90)
I have a question regarding the 030 Cache Control Register, if anyone would be
so kind as to enlighten me. I'm completing v2.0 of Amiga Intuition Based
Benchmarks, (AIBB), and have added the abiliity to manipulate the 030 caches
from within the program. Now, will someone explain the exact purpose of the
Write Allocate bit in respect to the Data Cache? [I'm fairly sure it should be
ON when the D-Cache is, from my limited experience with it]. I assume wheter
or not this bit is set makes no difference with regards to the Instruction
cache, which is read-only anyway. Also, here's an interesting development:
When doing a derivation of CSA's WritePixel benchmark (box-drawing using
SetAPen() / WritePixel() ), running with the Data cache OFF and the Instructio
cache ON is faster than running with both caches ON. Any comments as to this
development?
--LaMonte
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