wemmp@cutmcvax.cs.curtin.edu.au (Peter Wemm) (11/01/90)
Well call me crazy, but this is the plan: 512k kickstart ram, 1.5meg $c00000 ram (fast), eventually fat agnus+1 meg chip. But first I need some info (dave?).. 1) Can I get away with putting about 15 - 20 ns delay between the cpu address lines (a23-a18) and the motherboard 2) Where on earth can I get hold of the current pal equations and/or schematics?? The machine in question is a single-board pal machine (no daughterboard). My plan was to multiplex all two megs of ram through the top 256k (kickstart) and fake up a write enable line for it. The fat agnus (at first look) would need it's own private ram, getting it's addresses from the cpu rather than the ram address multiplexers. It would also have to over-ride the on-board clock generator. We have come up with a (messy :-) circuit that makes quite a few assumptions about how the system works, going from tracing the motherboard (yech..). All we need to know is if there is an easier way of doing it.. (there must be..) Can anyone please send me the equations, feedback, and/or where I can get detailed Info from?? Is there anyone in OZ that I can loan a copy of the schematics from?? thanks. -- Peter Wemm ------------------------------------------------------------------------------ wemmp@cutmcvax.oz.au (wemmp@cutmcvax.oz or ..!munnari!cutmcvax.oz.au!wemmp) "VMS is a text-only adventure game. If you win you can use unix." - w.davidson