gad@linac.fnal.gov (Greg A. Deuerling) (11/22/90)
I have recently finished a hardware project for my 2000. The project only takes up half of my proto-board. I have a couple 1Meg X 8 SIP's laying around and I'd like to put them on the un-used proto area. My problem is I can't figure out how to generate refresh for the ram on the proto board. I know there are 4 refresh cycles at the start of a Horizontal Scan. One scan is around 63 micro- seconds. I can easily build a circuit that would initiate a refresh, but how do I sync up to the start of the Horizontal Scan ???? The Hardware Reference Manual explains all of this but it tells you nothing on how to sync to the Horizontal Scan. Any help at all would be greatly appreciated. Thanks. GAD.
daveh@cbmvax.commodore.com (Dave Haynie) (11/27/90)
In article <3024@linac.fnal.gov> gad@linac.fnal.gov (Greg A. Deuerling) writes: >I have recently finished a hardware project for my 2000. >The project only takes up half of my proto-board. I have >a couple 1Meg X 8 SIP's laying around and I'd like to put >them on the un-used proto area. My problem is I can't >figure out how to generate refresh for the ram on the >proto board. I know there are 4 refresh cycles at the >start of a Horizontal Scan. There are Chip RAM refresh cycles generated on horizontal scans. These apply only to Chip RAM; there is absolutely no way you can take advantage of them on the expansion bus. On the Amiga bus, refresh cycles are left up to the card designer. While some bus designs (such as the IBM PC bus) have a refresh cycle actually driven on the bus, the Amiga bus doesn't. First of all, it's often possible to build a memory design that hides all refreshes from the bus. Secondly, most refresh schemes tend to be architecture dependent -- for instance, the Chip bus refresh driven by the original (512K) Agnus chip doesn't properly refresh 4 Meg (as in 1 Meg x 4) density devices. So you have to do your own refresh. At Zorro II bus speeds, it's possible with 150ns or faster DRAM to run both a CPU cycle and a refresh cycle in the same bus cycle, much in the same way the Chip bus runs an Agnus and a CPU cycle in the same 560ns 68000 cycle time frame. The easiest form of refresh to implement by hand is CAS before RAS refresh, which uses the internal address counters of the DRAM rather than a system defined address counter. Early boards, like the A2052, ran one refresh cycle for every single bus cycle, regardless of whether or not it was necessary. I don't recommend that; that's about the only way to make a simple 2 Meg board draw 3 Amps. >Thanks. GAD. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy ONLY 230 MILES TO GO